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UDB Timer connected to HFCLK directly, an external CLK (TCXO 32MHz) used.
When compile it always get this warning.
Warning: sta.M0019: MainBoard_timing.html: Warning-1366: Setup time violation found in a path from clock ( CyHFCLK ) to clock .
And here is the attached html generated by the compiler.
So my question is :
#1. what is the problem of this? it said setup time, I am not quite understand this.
#2. As the timer is sensitive to the accuracy and precision, so any performance impact?
Solved! Go to Solution.
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Hi
Please refer to the below appnote for understanding on timing analysis .Yes it may have an impact on the performance if timing requirements are not met.
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Hi
Please refer to the below appnote for understanding on timing analysis .Yes it may have an impact on the performance if timing requirements are not met.