Problem with the SAR ADC on PSOC4 -- limited to VDD/2?

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Anonymous
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Hello. I am having trouble with the SAR ADC. It doesn't seem to be able to measure voltages above VDD/2. I'm using it in single ended, signed input mode with internal 1.024v bypassed (with the appropriate cap in place). I've verified that Vref is about 1.024v. The ADC configurator says my range should be 0-2.048v. 

   

But at 3.0v VDD, a 2v triangle wave starts at about 0.3v (it shows a sharp corner on the triangle, not saturation) and then shows a decreased gain at 1.4v and stops completely at 1.6v. At 2.6v VDD, the max drops to 1.4v and the offset shrinks, while at 3.6v VDD, the max goes up to 1.8v and the offset grows to 0.4v.

   

Has anyone else seen this behavior before? Should I configure my SAR differently somehow? I can't seem to find any of these limitations mentioned in the documentation...

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1 Solution
Anonymous
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OK, we solved the problem, but don't know why it works. The solution was:

   

1. Switch one of our opamps from OA1 to the previously-unused OA2. This seemed to make the switching fabric choose a less complex path for our signal

   

2. Reassigned a pin on our FRAM component (FHOLD, which doesn't actually connect to the chip) from p3.3 to p1.0.

   

Only by doing both of these things does the problem clean up.

   

The settings were quite clear -- we were set for a 0-2.048v range, and parasitics are pretty minimal. This seems to have been an issue of the switching fabric somehow mixing our signal with something, draining it to somewhere, or ?

   

A bit scary and very confounding.

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4 Replies
Vasanth
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250 sign-ins 500 solutions authored First question asked

Hi Jim,

Could you attach your project so that we can have a look into it?

Best Regards,
VSRS

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Anonymous
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OK, how can I send you the project confidentially. I don't want to put our source code up on the web for anyone to see.

   

I'm also attaching an image showing what happens when we drive a triangle signal into bufin. The two waves you see are the analog value of bufout and the ADC readings, both during sampling.

   

 

   

 

   

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Anonymous
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Since you are limited to VDD/2, I would suggest double checking the settings; The VDD/2 is a limit for one of the SAR ADC settings for range measurement limits. Also, from your graph of the data, it looks pretty accurate besides a difference of small constant offsets; I would attribute the x-delay to sample-time-delay, but not sure about the peaks being different amplitude. Possibly there is some resistance/parasitic components on your ADC readings.

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Anonymous
Not applicable

OK, we solved the problem, but don't know why it works. The solution was:

   

1. Switch one of our opamps from OA1 to the previously-unused OA2. This seemed to make the switching fabric choose a less complex path for our signal

   

2. Reassigned a pin on our FRAM component (FHOLD, which doesn't actually connect to the chip) from p3.3 to p1.0.

   

Only by doing both of these things does the problem clean up.

   

The settings were quite clear -- we were set for a 0-2.048v range, and parasitics are pretty minimal. This seems to have been an issue of the switching fabric somehow mixing our signal with something, draining it to somewhere, or ?

   

A bit scary and very confounding.

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