1. does BLE 5.0 can work with BLE 4.1 host device?
Yes, PSoC 6 BLE is 5.0 complaint, and as per BLE 5.0 Core Specification, 5.0 low energy devices will be compatible with 4.2, 4.1 and 4.0 BLE devices.
2. Any info on basic info like number of pins and package? One of my app requires more than 38 GPIO pins.
No worries, up to 104 GPIOs are supported in 124 BGA package. For more details on other package options, please stay tuned for updates on the datasheet which will be posted in the next couple of weeks.
3. Is the USB supported 2.0 or 3.0 or 3.1? What all types of transfer supported for USB like Interrupt, Bulk, Isochronous?
Will support USB 2.0 Full-Speed Dual-role Host and Device.
4. Does single core offering in PSOC 6 support USB, BLE, CapSense on the same chip? Yes.
5. If I use this chip for isolated SMPS design like flyback or half bridge, Can I directly connect Aux winding output voltage here such as internal regulator will take care of regulation? Some of the chips I used are sensitive to higher ripple.
I'm afraid the internal regulator will not be able to support large ripples, although I would suggest you to wait for the datasheet to check the exact numbers. Also, for your reference, the normal power supply range is 1.7 to 3.6V.
4. Does single core offering in PSOC 6 support USB, BLE, CapSense on the same chip?
Sorry for misreading this, only the connectivity line devices (CY8C63) contain BLE which doesn't include USB (only dual core devices contain CapSense in addition to BLE). Please consider this as preliminary data and refer to the datasheet once it's released for the latest information.