STMf324xx Very Long Deep Sleep (using 1 Hz ck_spre)

[dast_1961951]

Found what appears to be an issue with sleeping for very long periods (> (65535/32768*16) seconds).

stop_mode_power_down_hook() calls a function platform_rtc_enter_powersave(), which has the following code:

    /* Change the clocking state of the RTC, so it ticks every 1.25ms while cpu is sleeping - 800Hz clock */

    stm32f2_rtc_change_clock( &current_clock_state, CLOCKING_EVERY_1p25MSEC );

This code changes the RTC divider input to tick ever 1.25 millisecond instead of every 1 second.   Because the RTC WKUP divider is set to CK_SPRE_CLOCK_SOURCE_SELECTED, (basically the result of all the RTC clock dividers, the WKUP clock ticks every 1.25 ms.  

The way I noticed this is as follows:

I had a loop that delay for 600s.  The delay still functioned correctly, but the MCU would wake approximately every 800 ms.

Doing the math, (600 * 1.25e-3) = 750 ms.   Which is pretty close to my observed wakeup frequency.  When I removed the stm32f2_rtc_change_clock() call, the RTC only woke up at the appropriate time.

[dast_1961951]

Keep in mind platform_rtc_abort_powersave() also expects the spre clock to be ticking each 1.25ms.  So above will lead to a lot of RTC inaccuracy.  A fix/alternate function would likely just exit powersave without adjusting the rtc.

[dast_1961951 · Accepted solution]

After looking closer at this issue, I've decided the change is risky and will involve allowing more RTC drift/inaccuracy than I'd like.  I will choose instead to limit deep sleep intervals to 30 seconds and revisit later.