Moving to the BLE forum.
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The PUART FIFO for RX and TX is 16 bytes. There's no way to reconfigure this as it is a hardware FIFO.
The hardware user guide has useful information about the PUART: WICED Smart Hardware Interfaces. It notes that without the use of flow control, it is the application's responsibility to service the FIFO before the TX FIFO empties or before the RX FIFO fills to prevent data loss.
In our application, we try 16 bytes for sending to other site of component by using PUART; however, in Rx,
we only get 15 bytes always and the last byte is always truncated or missed? is any idea about this issue or
the FIFO size is 15 bytes only?
Does lowering the baud rate help? Is it the same on both sides? And btw, puart will not work when the chip is sleeping.
Baudrate is same as 9600-bps.
I use a PC UART tracer to role-play as Rx to check data sent from device PUART.
A data size of 100 bytes is rather long and you may like to consider implementing flow control. You can also set the water mark on the tx side to 0 so that it trigger a call back once the fifo buffer is empty.