PSoC5LP : PICU interrupt in Hibernate mode

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Dear Sirs and Madams,

Please tell us about PICU interrupts.

When the PICU interrupt was in the pending state just before entering hibernate mode,

If you enter hibernate mode in that state, interrupts are enabled, so I think that you will exit hibernate mode and shift to active mode.

Is the above understanding correct?

According to register TRM, the CYREG_PICUx_INTSTAT register is "Read to Clear".

At this time, if the "CYREG_PICUx_INTSTAT" register is read and the contents of the register are cleared before entering hibernation,

will the pending state of the interrupt be cleared and will it stay in hibernate mode?

("x" is the port number to interrupt the PICU)

Or will it stay in hibernate mode if the interrupt factor pending with CYREG_NVIC_CLRPEND0 is cleared?

The reason for the above question is that the system uses RTOS and does not use the PSoC API as it is for enabling and disabling interrupts.

Therefore, We are asking the above questions.

Regards,

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AikoO_51
Moderator
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Moderator
100 sign-ins First question asked 50 solutions authored

If there are pending interrupts before getting hibernate mode, they would keep and be stored until wake-up.

However such operation which is maintained interrupts during hibernate mode is unexpected, so it might have something wrong with interrupts or wake-up.

It's recommended to clear all pending interrupt before entering into Deep sleep/ Hibernate mode.

Aiko Ohtaka
Infineon Technologies

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3 Replies
AikoO_51
Moderator
Moderator
Moderator
100 sign-ins First question asked 50 solutions authored

If there are pending interrupts before getting hibernate mode, they would keep and be stored until wake-up.

However such operation which is maintained interrupts during hibernate mode is unexpected, so it might have something wrong with interrupts or wake-up.

It's recommended to clear all pending interrupt before entering into Deep sleep/ Hibernate mode.

Aiko Ohtaka
Infineon Technologies
MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Aiko-san,

We try to clear and confirm all pending interrupts before going into hibernate mode.

Regards,

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Aiko-san,

I've tried various test circuits, but it may be important to clear all interrupts.

However, this phenomenon is due to multiple factors.

It is difficult to solve by just clearing all these interrupts.

Thank you,

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