How to change the Out of Band interrupt GPIO for CY43455 in wiced SDK

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YaBh_4672321
Level 3
Level 3
25 replies posted 10 replies posted 10 sign-ins

Hi,

In out Hardware design we are using GPIO 5 of CY43455 as OOB interrupt. But we are not sure who to configure the same in software.

We have updated wwd_bus_sdio_set_oob_interrupt() function as follows:

{

    VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, SDIO_GPIO_SELECT, (uint8_t)1, (uint32_t) 0xF ) );

    VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, SDIO_GPIO_OUTPUT, (uint8_t)1, (uint32_t) 0x05 ) );

    /* Enable GPIOx (bit x) */

    VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, SDIO_GPIO_ENABLE, (uint8_t)1, (uint32_t)0x10 ) );

    /* Set GPIOx (bit x) on Chipcommon GPIO Control register */

    VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, CHIPCOMMON_GPIO_CONTROL, (uint8_t)4, (uint32_t)0x10 ) );

}

But this does not seem to work.

What is the correct register configuration to enable GPIO 5 as OOB. Also apart from this is there any thing else required?

Regards,

Yash

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1 Solution

Hello:

Better to contact your local Cypress/Infineon representatives to support this feature and get a confirmed answer .

We only can find a mask flag in firmware, but have no successful experience .

View solution in original post

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10 Replies
Zhengbao_Zhang
Moderator
Moderator
Moderator
250 sign-ins First comment on KBA 10 questions asked

Hello:

  from my understand:

{

VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, SDIO_GPIO_SELECT, (uint8_t)1, (uint32_t) 0xF ) );   // keep 0xf

VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, SDIO_GPIO_OUTPUT, (uint8_t)1, (uint32_t) 0x00) );  // keep 0x0

/* Enable GPIOx (bit x) */

VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, SDIO_GPIO_ENABLE, (uint8_t)1, (uint32_t)0x20 ) );  // if GPIO5, change to 0x20

/* Set GPIOx (bit x) on Chipcommon GPIO Control register */

VERIFY_RESULT( wwd_bus_write_register_value( BACKPLANE_FUNCTION, CHIPCOMMON_GPIO_CONTROL, (uint8_t)4, (uint32_t)0x20) );// if GPIO5, change to 0x20

}

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Hello,

Thank you for your response but those GPIO configuration does not seem to work.

Can you please confirm that those are the only changes that we need to make or that are any other changes required to change the OOB gpio from 0 to 5?

Thanks and Regards,

Yash

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Hello:

   From the code comments it seems the boards are designed to use GPIO0 or GPIO1 currently.

by the way what is the reason we need to use GPIO5 to replace GPIO0 or GPIO1.

/**

* Get OOB interrupt pin (WLAN GPIO0 or GPIO1)

*/

extern uint8_t host_platform_get_oob_interrupt_pin( void );

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Hi,

The datasheet does not mention any such limitation. Can you please consult the design team and confirm if this is the case?

We are using GPIO5 for our layout feasibility.

Regards,

Yash

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We will create internal case to find correct answer.

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Hello:

Which version of the WICED are you using now ?

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Hi,

We don't have a version of WICED at hand because we are using the example project from NXP IMXRT1060 and have ported it over to our Kinetis-64 board.

Is this related to SDK version?

Regards,

Yash

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No, I just need to know the information.  And we didn't have any experience with OOB on GPIO5.

So my suggestion  is to change the INT pin to GPIO0 or GPIO1 as code said .

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Hi,

Can you please confirm internally if this is the only option we have?

Regards,

Yash

0 Likes

Hello:

Better to contact your local Cypress/Infineon representatives to support this feature and get a confirmed answer .

We only can find a mask flag in firmware, but have no successful experience .

0 Likes