EXTCLK and External Pin Output

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NiBu_4687336
Level 5
Level 5
5 solutions authored 50 replies posted 25 replies posted

Hi.

My project uses a PSoC 6 to drive an external ADC device. The ADC requires a clock source, and I'm using the PSoC 6 to generate that clock via a PLL and the one CLK_HFn clock source that can be connected to an external pin (CLK_HF5 on the CY8CPROTO-062-4343W). This works well, except that we also want to drive the PSoC 6 from an external VCTCXO clock source on EXTCLK.

When I enable EXTCLK, though, the Device Configurator will no longer allow me to select an output pin for my ADC clock.

Is it possible to have both an external clock input (on EXTCLK) and and external clock output in the same design?

Thanks,

-Nick

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Ekta_N
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750 replies posted First like given 250 solutions authored

Hello Nick,

I got the same error when trying to make the same setting in Device configurator 2.1.

But with Device configurator 2.2 (That comes with Modustoolbox 2.2) I was able to route the EXTCLK to an output pin by making the following settings:

1. Under the Systems Tab enable the EXTCLK, Pin0[0] is being used.

2. Source clock for Path Mux 5 has been set to EXTCLK.

3. Source clock for the CLK_HF5 has been set to CLK_PATH5.

4. For CLK_HF5 Clock Output is set P0[5]. (Please note that you need to enable the p0[5] pin under the pins tab asnd set the drive mode for this pin as strong drive, input buffer off).

With the above settings I did not get any error. Also please note that you should not use the same pin for both input and output of EXTCLK.

Thus, I would suggest you to upgrade to Modustoolbox 2.2.

Please refer to the following KBA for more details: Route Internal Clock Out to a Pin in PSoC 6 – KBA224493

In case you do not want to upgrade you can route the EXTCLK as input to a PWM and route the output of PWM to an output pin. You can set the period of PWM depending on the required frequency. The maximum output frequency from the PWM = Input frequency / 2.

Best Regards

Ekta

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Ekta_N
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750 replies posted First like given 250 solutions authored

Hello NiBu_4687336

Can you please share the configurations that you had made in the device configurator for both the cases (case 1: when you are using PSoC 6 to generate the clock and case 2:  when you are are driving the PSoC 6 using an EXTCLK)

It would be really helpful if you could attach your Modustoolbox project.

Please note that it is possible to use EXTCLK source clock for either the PLL or FLL, or can be used directly by the high-frequency clock

Best Regards

Ekta

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Hi EktaN_26​.

I've attached a .modus file that demonstrates the issue. The associated connection diagram is below.

If EXTCLK is enabled and assigned to a pin, then CLK_HF5 cannot be assigned to a pin - the selection dialog for Clock Output lists no available pins.

If EXTCLK is disabled, CLK_HF5 can be assigned to either P0[0] or P0[5]. If EXTCLK is then enabled, it can be assigned to either P0[0] or P0[5], at which point a warning is displayed for CLK_HF5 saying, "The current personality does not support the following connection(s): P0 digital_out."

Thanks,

-Nick

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Ekta_N
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750 replies posted First like given 250 solutions authored

Hello Nick,

I got the same error when trying to make the same setting in Device configurator 2.1.

But with Device configurator 2.2 (That comes with Modustoolbox 2.2) I was able to route the EXTCLK to an output pin by making the following settings:

1. Under the Systems Tab enable the EXTCLK, Pin0[0] is being used.

2. Source clock for Path Mux 5 has been set to EXTCLK.

3. Source clock for the CLK_HF5 has been set to CLK_PATH5.

4. For CLK_HF5 Clock Output is set P0[5]. (Please note that you need to enable the p0[5] pin under the pins tab asnd set the drive mode for this pin as strong drive, input buffer off).

With the above settings I did not get any error. Also please note that you should not use the same pin for both input and output of EXTCLK.

Thus, I would suggest you to upgrade to Modustoolbox 2.2.

Please refer to the following KBA for more details: Route Internal Clock Out to a Pin in PSoC 6 – KBA224493

In case you do not want to upgrade you can route the EXTCLK as input to a PWM and route the output of PWM to an output pin. You can set the period of PWM depending on the required frequency. The maximum output frequency from the PWM = Input frequency / 2.

Best Regards

Ekta

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Hi EktaN_26​.

I've upgraded to ModusToolbox 2.2, but I don't see any change in the problem. Note the version in the title bar, and the tool-tip showing the warning. EXTCLK is connected to P0[0], and CLK_HF5 is connected to P0[5]. Pin P0[5] is set to strong drive, input buffer off.

CLK_Hf5.png

Thanks,

-Nick

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Still no answer to this question.

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Ekta_N
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750 replies posted First like given 250 solutions authored

Hello Nick,

I have configured design.modus according points stated in my previous reply and I was able to make the settings without the warning being generated as in your case.

pastedImage_1.png

and

pastedImage_2.png

I have attached the design.modus file with the above configuration.  Could please open the file and see if you are getting the same error?

Best Regards

Ekta

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Hi EktaN_26​.

All I have to do is open the file you attached, and this is what I get:

Capture.PNG

Also, when I save the file, without making any changes, the warning changes to an error. This occurs with my file as well.

What version of Device Configurator are you using? And what does your devicesupport.xml look like? Mine is an empty file.

I've attached my file for comparison.

Thanks,

-Nick

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Just keeping the thread alive, hoping for an answer.

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Nick,

I configured a MTB 2.2 project with your clocking configuration:

  • EXTCLK (in) assigned to P0[0]
  • CLK_HF5 (out) assigned to P0[5].

pastedImage_2.png

No errors in the build.

Len

Len
"Engineering is an Art. The Art of Compromise."
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Hi LePo_1062026​.

Thanks for the reply.

It's great that you're able to do what I can't, but with all due respect, we already knew that two weeks ago. I'm no closer to solving the problem now than I was then.

It appears from your screen shot that you're not using the production Windows version of Device Configurator. How about we start there?

I'm using Device Configurator version 2.20.0.3158 on Windows. I've also tried the Linux version (same version number) with the same result.

Thanks,

-Nick

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Nick,

I wasn't sure I could be of help.  I figured I would try to reproduce your results.

However, you only supplied the .modus file and not the whole project.   It might be possible that something else in your project is disallowing P0[5] for the clock out purpose.

By the way, here is the Device Configurator version I was using on a Windows 10 system.

pastedImage_0.png

Len

Len
"Engineering is an Art. The Art of Compromise."
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Hi LePo_1062026​.

Sorry - I didn't mean to sound so grumpy. I appreciate the help. 🙂

I was able to reproduce the problem using a canned Cypress application.

This afternoon, I downloaded ModusToolbox 2.2 to a Linux (Ubuntu 16.04) machine to see if it behaved differently. After launching MTB, I clicked the New Application link in the Quick Panel, selected the CY8CPROTO-062-4242W BSP, and then checked the Fault Handling application and clicked Create.

When the Project Creator had finished doing its thing, I launched the Device Configurator from the Quick Panel link. I enabled EXTCLK and assigned it to pin P0[0], then enabled CLK_HF5 and clicked the Clock Output button. I was presented with an empty list from which to choose:

Capture.PNG

This is one of the ways the problem manifests itself. If I disable EXTCLK, I can assign a pin to CLK_HF5, then re-enable EXTCLK and assign it a pin, but then I get the warning/error that CLK_HF5's CLK_HF-1.1 personality doesn't support the connection on P0[5].

The reason I thought you might be using a different version of Device Configurator is that your clock schematic diagram display is different than mine:

Capture.PNG

My resource tiles show only the resource name; yours show the name, plus the configured frequency and precision. I can't find any option to change the display format.

The problem I'm seeing is consistent between two MTB installations on two machines running different OSes. But no one else has the problem. I'm not sure what's going on.

-Nick

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Nick,

It appears to be a strange issue.

I did notice something about your configuration that I get warnings on.  It complains that "The device does not support disabling the resource 'PATH_MUXx'"

pastedImage_0.png

Len

Len
"Engineering is an Art. The Art of Compromise."
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