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Hi all,
I am just now trying to learn how to use the Verilog functionality of PSoC. I just had one question, if I made a component and write Verilog code for it; lets say I want to read the output of the component on the main loop in C, hw would I set the component so that I could read it by a command such as component_Read() for example.
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- Labels:
-
PSoC 5 Device Programming
-
PSoC 5LP
- Tags:
- verilog
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Hi,
I'm afraid that I was too slow.
Although odissey1-san has posted the answer,
as I also created a sample, let me post it anyway 😉
As far as I know, I could describe a component with Verilog HDL,
I could only generate a symbol for it.
So I need either using Control_Reg and Status_Reg to directly write/read data,
or connect other component(s) to assign data into the component and/or extract data from it.
As usual I tried with CY8CKIT-059.
First I wrote a simple verilog in the Workspace > <project> > Components Tab, using Add Component Item...
Then I create a symbol for it
Then I created a schematic
Pins
main.c
===================
#include "project.h"
#include "stdio.h"
#define STR_LEN 32
char str[STR_LEN+1] ;
void print(char *str)
{
UART_PutString(str) ;
}
void cls(void)
{
print("\033c") ; /* reset */
CyDelay(20) ;
print("\033[2J") ; /* clear screen */
CyDelay(20) ;
}
void splash(char *prog_name)
{
cls() ;
if (prog_name && *prog_name) {
print(prog_name) ;
}
print(" (") ;
print(__DATE__) ;
print(" ") ;
print(__TIME__) ;
print(")\n") ;
}
void init_hardware(void)
{
CyGlobalIntEnable; /* Enable global interrupts. */
UART_Start() ;
}
int main(void)
{
uint8_t in, out ;
int i ;
init_hardware() ;
splash("5LP Verilog Test") ;
for(;;)
{
for (i = 0 ; i < 0x100 ; i++) {
in = i & 0xFF ;
in_data_Write(in) ;
out = out_data_Read() ;
snprintf(str,STR_LEN, "0x%02X -> 0x%02X\n\r", in, out) ;
print(str) ;
CyDelay(1000) ;
}
}
}
===================
The result Tera Term log was
moto
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CaDu,
That, of course, depends on the component internals. If the component is a simple Verilog w/o using a Datapath, then simplest would be to add output bus to the component and use a Status Register outside the component to read the bus data.
It is possible to instantiate a Status register inside a Verilog component, and read it directly. Attached is a demo project showing accessing Control and a Status registers inside a custom component using API call.
/odissey1
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Hi,
I'm afraid that I was too slow.
Although odissey1-san has posted the answer,
as I also created a sample, let me post it anyway 😉
As far as I know, I could describe a component with Verilog HDL,
I could only generate a symbol for it.
So I need either using Control_Reg and Status_Reg to directly write/read data,
or connect other component(s) to assign data into the component and/or extract data from it.
As usual I tried with CY8CKIT-059.
First I wrote a simple verilog in the Workspace > <project> > Components Tab, using Add Component Item...
Then I create a symbol for it
Then I created a schematic
Pins
main.c
===================
#include "project.h"
#include "stdio.h"
#define STR_LEN 32
char str[STR_LEN+1] ;
void print(char *str)
{
UART_PutString(str) ;
}
void cls(void)
{
print("\033c") ; /* reset */
CyDelay(20) ;
print("\033[2J") ; /* clear screen */
CyDelay(20) ;
}
void splash(char *prog_name)
{
cls() ;
if (prog_name && *prog_name) {
print(prog_name) ;
}
print(" (") ;
print(__DATE__) ;
print(" ") ;
print(__TIME__) ;
print(")\n") ;
}
void init_hardware(void)
{
CyGlobalIntEnable; /* Enable global interrupts. */
UART_Start() ;
}
int main(void)
{
uint8_t in, out ;
int i ;
init_hardware() ;
splash("5LP Verilog Test") ;
for(;;)
{
for (i = 0 ; i < 0x100 ; i++) {
in = i & 0xFF ;
in_data_Write(in) ;
out = out_data_Read() ;
snprintf(str,STR_LEN, "0x%02X -> 0x%02X\n\r", in, out) ;
print(str) ;
CyDelay(1000) ;
}
}
}
===================
The result Tera Term log was
moto