2 Replies Latest reply on Oct 13, 2020 4:14 PM by BoTa_264741

    ADC_SAR - Filter - VDAC streaming demo using DMA

    BoTa_264741

      Hi,

      In the previous post it was shown how to use DMA with DelSig-ADC and Filter (PSoC5).

      DelSig_ADC - Filter - VDAC streaming demo using DMA

       

      Provided below is similar project, but utilizing ADC_SAR instead of the DelSig-ADC.

       

      Provided below are 3 projects:

       

      1. SAR-Filter-VDAC_01c_stripped.cydsn

      Standard ADC_SAR-Filter-VDAC demo, exemplifying the ADC_SAR issues:

         * ADC_SAR is not performing correctly in the differential mode. The ADC_SAR output is always unsigned (0-4095) no matter if input is configured for differential or single mode (the DelSig-ADC correctly outputs -2048 to 2047 in the differential mode).

         * The Filter input expects signed 16-bit data, but ADC_SAR produces only 12-bit unsigned data. This 4-bit offset can't be corrected by DMA alone.

       

      As a result, a simple DMA transfer ADC-Filter-VDAC results in very weak output, 1/16 of the VDAC8 full output scale.

       

      2. SAR-Filter-VDAC_signed_FIFO_02a.cydsn

      Enhanced demo, where the ADC_SAR output is first converted from unsigned to 2's compliment, and then scaled up by 4 bits to make a 16-bit signed data, which is captured by the FIFO and transferred to the Filter by DMA1. The Filter output is also signed, so it converted back to unsigned (uint8) using external logic, and transferred to VDAC using DMA2 with chained TDs.

       

      3. SAR-Filter-VDAC_unsigned_FIFO_02a.cydsn

      Simplified demo, where the ADC_SAR output is NOT converted from unsigned to 2's compliment. It is just scaled up by 3 bits to make a 15-bit unsigned data, which is captured by the FIFO and transferred to the Filter by DMA1. The filter output is UN-signed, so it can be sent directly to VDAC8 by DMA2. The Filter gain is doubled to compensate for amplitude loss.

       

      /odissey1

       

      Project uses several custom Community components, which are included in the project. A full version of the project has sine generator included. A stripped version of the project has sine generator removed. It can be used if external function generator is available.

           * ADC_SAR_ex: Re: Best Approach: Implement DMA on 16bit Timer or 2 Status Registers?   (included in the project)

           * FIFOin: Re: Best Approach: Implement DMA on 16bit Timer or 2 Status Registers? (included in the project)

           * BusConnect: BusConnect: virtual interface for digital hardware bus (included in the project)

           * WaveGen8 (RAM-DMA-VDAC8 wave generator, included in the project)

           * QuadDecoder_SW: Re: Quad Decoder with Button Switch component for rotary shaft encoders

           * DDS32: Re: DDS24: 24-bit DDS arbitrary frequency generator component

           * optional PSoC Annotation Library: PSoC Annotation Library v1.0

       

       

       

      Presented Below are screenshots from the "enhanced" project SAR-Filter-VDAC_signed_FIFO_02a.cydsn

      Figure 1. ADC_SAR-Filter page schematic. ADC result is converted from 12-bit unsigned to to 16-bit 2's complement. The Filter gain = 1.

      SAR-Filter-VDAC_signed_FIFO_02a_A.png

       

       

      Figure 2. Filter-VDAC page schematic. Filter result converted from 2's complement to 8-bit unsigned using DMA2 two chained TDs.

      SAR-Filter-VDAC_signed_FIFO_02a_B.png

       

      Figure 3. Optional signal (sine) generator for project testing. It is not included in the stripped version of the project, which requires external signal generator for testing.

      SAR-Filter-VDAC_signed_FIFO_02a_WaveGen.png

       

      Figure 4. Project annotation (made using optional PSoC Annotation Library v1.0 ). Note the ADC input bias is taken directly from the bias capacitor C12. This schematic is shared among all projects.

      SAR-Filter-VDAC_signed_FIFO_02a_KIT-059.png

       

      Figure 5. Cyan - 1 kHz ADC signal input, Yellow trace - VDAC output, Fuchsia - signal reference. Filter configured for LPF, Fc=5kHz, Gain=1.

      SAR-Filter-VDAC_signed_FIFO_02a_D1.png

       

      Figure 6. Cyan - 5 kHz ADC signal input, Yellow trace - VDAC output, Fuchsia - signal reference.. Filter configured for LPF, Fc=5kHz, Gain=1.

      SAR-Filter-VDAC_signed_FIFO_02a_D2_5kHz.png

       

      Figure 7. Cyan - 6 kHz ADC signal input, Yellow trace - VDAC output, Fuchsia - signal reference. Filter configured for LPF, Fc=5kHz, Gain=1.

      SAR-Filter-VDAC_signed_FIFO_02a_D3_6kHz.png

        • 1. Re: ADC_SAR - Filter - VDAC8 streaming demo using DMA
          BoTa_264741

          Continued...

          Projects:

          SAR-Filter-VDAC_unsigned_FIFO_02a.cydsn

          SAR-Filter-VDAC_unsigned_FIFO_02a_stripped.cydsn

           

          This is a simplified demo, using only unsigned input and output of the filter. The ADC_SAR output is NOT converted from unsigned to 2's compliment. It is merely scaled up by 3 bits to make a 15-bit unsigned data, which is captured by the FIFO and transferred to the Filter by DMA1. The filter output is UN-signed, so it can be sent directly to VDAC8 by DMA2. The Filter gain has to be doubled to compensate for amplitude loss. This approach shall work only if Filter is configured for Low Pass mode.

           

          The stripped version of the project needs external signal generator for testing.

          /odissey1

           

          Figure 1. ADC_SAR-Filter page schematic (project SAR-Filter-VDAC_unsigned_FIFO_02a.cydsn). ADC result is converted from 12-bit unsigned to to 15-bit unsigned. The gain of the Filter has to be doubled to compensate for 1/2 amplitude loss.

          SAR-Filter-VDAC_unsigned_FIFO_02a_A.png

           

          Figure 2. Filter-VDAC page schematic. Filter result directly transferred to VDAC.

          SAR-Filter-VDAC_unsigned_FIFO_02a_B.png

           

          Figure 3. 1 kHz sine input. Yellow trace - VDAC output; Cyan - ADC signal input (WaveGen output), Fuchsia - signal reference. Filter configured for LPF, Fc=5kHz, Gain=2.

          SAR-Filter-VDAC_unsigned_FIFO_02a_D1_1kHz.png

          Figure 4. 5 kHz sine input. Yellow trace - VDAC output; Cyan - ADC signal input (WaveGen output), Fuchsia - signal reference. Filter configured for LPF, Fc=5kHz, Gain=2.

          SAR-Filter-VDAC_unsigned_FIFO_02a_D2_5kHz.png

           

          Figure 5. 6 kHz sine input. Yellow trace - VDAC output; Cyan - ADC signal input (WaveGen output), Fuchsia - signal reference. Filter configured for LPF, Fc=5kHz, Gain=2. Notice correct output signal offset value (Vdda/2).

          SAR-Filter-VDAC_unsigned_FIFO_02a_D3_6kHz.png

          • 2. Re: ADC_SAR - Filter - VDAC8 streaming demo using DMA
            BoTa_264741

            Continued...

            Project:

            SAR-Filter-VDAC_01c_stripped.cydsn

             

            This is a standard demo, using direct transfer ADC - Filter - VDAC using DMA. Project demonstrates several issues:

            *   ADC_SAR not performing correctly in the differential mode. The ADC output is always unsigned 0-4095 no matter if ADC_SAR in single or differential mode.

            *   The Filter input expects signed 16-bit data, but ADC_SAR produces only 12-bit unsigned. As a result, VDAC output appears to be only 1/16 of whole scale (Gain=1).

            *   This approach shall work only if Filter is configured for Low Pass mode.

             

            Only stripped version of the project is provided, which needs external signal generator for testing.

            /odissey1

             

            Figure 1. ADC_SAR-Filter page schematic (project SAR-Filter-VDAC_unsigned_FIFO_02a.cydsn). ADC result is converted from 12-bit unsigned to to 15-bit unsigned. The  Filter Gain=4 (max allowed) to partially compensate for amplitude loss.

            SAR-Filter_VDAC_01b_A.png

             

            Figure 2. Filter-VDAC page schematic. Filter result directly transferred to VDAC.

            SAR-Filter_VDAC_01b_B.png

             

            Figure 3. 1 kHz sine input. Yellow trace - VDAC output; Cyan -  ADC signal input (WaveGen output), Fuchsia - signal reference. Filter Gain=4 (max allowed), LPF, Fc=5kHz, Gain=4. Notice small output amplitude (1V) and incorrect offset (0.5V).

            SAR-Filter_VDAC_01b_D1.png