Can you kindly try once more by setting the Comparator power to Low Power? Kindly let me know the behaviour you find.
The TFF appears to be operating properly. The issue is that you have tied the comparator output to the clock of the TFF.
At the offending spot of your scope plot, you can see that the comparator output (YELLOW) is toggling multiple times within a very short amount of time. This is causing multiple clock transitions at your TFF clock input. This causes potentially many toggles of the TFF output (BLUE). Given what is happening at your comparator output, this is the expected results of your TFF.
You need to better filter your input to the comparator. If you are using LINE AC from power as I suspect, it is notoriously noisy ALL points in the waveform. This is due to many reasons including load transitions and other Conductive Emissions (CE) of upstream equipment.
Your best bet is to place an external Low-Pass Filter on the input to the comparator with a corner frequency as close to 60Hz as you can tolerate. The down-side with any analog LPF is that the cap used introduce a time delay to the wave. This may make using a LPF in your case (power factor calculator) not practical.
Suggestion: Does your power factor (PF) calculation need to be made in FAST realtime? If you can take a 'long' view, you can take multiple immediate PF measurements and throw away any that do not match the target 60Hz. You can then average your PF measurements that match the 60Hz criteria. This is a SW implementation without any additional external HW.
If you can take the 'long' view, this is a practical approach since the power company is reasonably reliable for their output frequency.
Can I recommend an experiment to prove out your PF phase detection circuit?
- Remove the AC stimulus from the Vadc and Iadc.
- Insert a digital signal to Vadc at 60Hz 50% DC.
- Insert a second digital signal to Iadc at 60Hz 50% DC.
- Control the time delay (phase shift) of the second signal.
The digital square wave should be more friendlier to the Comparators
This test circuit should allow you to detect the frequency at 60Hz. If you change the frequency, it should reflect this frequency in your debugging display. This is to prove out the frequency detection part of the circuit without input noise. It will also help to detect if there are any issues placing the SYNC component after the Comparators.
By time delaying the second Iadc input, you can control the phase shift and prove if your circuit (and SW) can properly detect the correct phase.
Once you're convinced your circuit can detect 0 to 359 degs of phase shift, then you should be able to reapply the AC input stimulus.
I have connected external hardware hysteresis.Should I remove them ?
I'm assuming you're referring to the hysteresis on the comparators since your schematic doesn't show any external components.
You can leave the hysteresis. With a digital input it won't make a difference.
Sorry for the late reply.
It seems to be normal at tff output when I set comparator to ultra low power mode,but I need more days to observe because I still get the wrong value of frequency.Maybe it is because of that behavior which I just didn't capture.Any idea about it,please tell me.
Thanks your help.
I insert the sqaure wave to Vadc and Iadc and the wrong value still occured when waveform is from external wave generator.
Since the wrong value is still occurring there appears to be something wrong with the logic or your detection circuit.
By using a scope on each stage of the circuit you can verify proper HW operation.
If the HW is operating to design, then there may be a SW processing issue.
If your screen shot, which shows 80khz is the sampling rate of the logic or scope, then you may wish to up your sampling rate, or use peak detect on your scope acquisition, should that be available. I suspect you are getting noise spikes and your comparators are sending them through. Roughly, you will need about 10 times the frequency you wish to see correctly in order to see the basic information you want. In this case, you need to narrow down your trigger and sample at 12 mhz to 20 mhz or better.
If you are using 80khz, then frequencies of 160khz, 320khz, 640khz, etc. will look like slower frequencies. Nyquist and ADC sample aliasing comes in to bite you here. I have had a beautiful 20khz sine wave from a 2mhz input signal on a scope due to aliasing.
By using synchronization FF's, you cause the counter signal to ignore intermediate transitions due to noise, which a previous poster pointed out is being hinted at in your scope/logic shot. That settled down your results, but probably not eliminated your problem.
To "fix" your problem, I would suggest extra power supply filtering on the analog system, or a very small capacitor on the input to the PSOC. Try 10pf -100pf or so on the input (assuming 60hz) to filter the noise out. Use a 100 ohm resistor in series with the input, making an R/C filter. You might be surprised at the results.
I will try to reproduce your result shortly.
I've noticed a number potential issues with your latest TopDesign:
Your configuration for the RC filter does not work.
I've modeled your circuit and performed an AC analysis.
Below is the AC response from 1Hz to 10KHz. No LF cutoff for IN1.
This circuit is a correct LPF for your situation.
Here is the LPF response.
Note: Using the series resistor of 10K and the parallel cap of 4.7us your corner frequency (-3dB) is 3.38Hz. This means at 60Hz you have a 20dB Loss. This means an input voltage of 3V appears as 0.3V at the comparator.
You might want to lower the resistor value or the cap value. For example if you keep the 10K resistor you just need a 270nF cap to get a corner frequency of 60 Hz.
You placed a 150K resistor for external hysteresis. However you have also configured the Comparator for internal hysteresis. By "adding" the external resistor might diminish the hysteresis voltage. Suggestion: Eliminate the external hysteresis and only use the internal one.
Asynchronous Comparator Output into a Synchronous Circuit
In your circuit you did not use the "Sync" option. I believe this is the reason you are getting the following issue you circled.
This is occurring because the timing of the minimum setup and hold times to the compare inputs for the Timers is not adhered to.
Then add the "timer_clk" to the clock input that appears on the comparator components.
Here is a new input front-end circuit with the new RC, hysteresis resistor removal and the "Sync" option.
I've got your project loaded on my Cy8CKIT-059.
When you get
for TFF output, what are you using for Vadc input? Sinewave or Digital (0V to 5V)?
I'm using a Digital input (0V to 5V) for both Vadc and Iadc. No issue at TFF output for about an hour so far.
You'll be glad to know that with a Sinewave source (0V to 4Vpp) I've been able to reproduce your results on the TFF output.
Sadly, it appears to be a problem with the Comparator resource. This is even true with the "Sync" enabled.
I'm gathering more data and submitting this as a example project for Cypress to weigh in on.
The the issue that I am seeing with the Comparator does not appear to be fixable.
However, I'm also working on a work-around for your application.