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Hi,
Onto our FX2LP18 based board, we use the GPIF and SlaveFIFO mode where IFCLK is used.
The IFCLK will be connected to 3 components : one FPGA, one CPLD and potentially another FPGA (Daughter Board thoufh a FMC connector).
Do we need to bufferise the IFCLK in such condition ? Is the output capability of the FX2LP18 is enought to drive the 3 components ?
Thanks.
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Hello,
We have not characterized this data. So I cannot guarantee you the proper functionality as individual current ratings and configuration of the device IO pins needs to considered.
Also, if 3 devices are connected to FX2LP18 for GPIF/Slave FIFO mode operation, FX2LP18 can only interact with one device at a time while the other 2 devices interface pins should be idle.
In this condition, if the other 2 devices CLK input pin is tri-stated/high impedance, the IFCLK can be connected to these devices.
Thanks,
Yatheesh
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Hello,
Can you please let me know if you require the IFCLK to provide clock to all the three devices at a time or one at a time?
If only one device is clocked at a time and the corresponding input pin of the other two devices is tri-stated, then you can use the IFCLK pin as stated.
Thanks,
Yatheesh
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HI,
All the 3 at a time potentially.
Thks
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Do you recommand to use 0 delay CLock buffer like : LMK1C1103 - NEW - 3-channel output LVCMOS 1.8-V buffer
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Hello,
Yes, that will do.
Also, can you please let me know the purpose of connecting the IFCLK to all the three devices? Is it to interface them with FX2LP FIFO or to just clock the devices.
If you need to just clock the devices, then you can also consider taking the output from the crystal directly or use the CLKOUT pin of the FX2LP which is the output of internal PLL.
Thanks,
Yatheesh
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The IFCLK is used in GPIF mode for FPGA download.
The IFCLK is also used in SlaveFIFO mode for FPGA communication.
Currently in the CPLD there is no usage of the IFCLK (just in case we need to clock something).
Perhaps better to use CLK_OUT to connect to CPLD ?
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Hello,
If there is no data communication to synchronize between FX2LP and CPLD, you can use the CLKOUT from FX2LP.
The CLKOUT is general used to clock FPGAs connected to FX2LP.
Please note that the CLKOUT frequency will be equal to the FX2LP CPU frequency i.e. 12/24/48 MHz, depending on the frequency selected using the CPUCS register (bits CLKSPD1 and CLKSPD0) of FX2LP.
Thanks,
Yatheesh
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But We are agree : IF_CLK is the good signal to be used for GPIF and SLAVEFIFO onto FPGA side ? Right ?
Onto the CPLD, CLK is there perhaps to synchronized some DATA coming from FX2LP18 … CLK_OUT can do the same ? CLKOUT and IFCLK are synchronous ?
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Hello,
IF_CLK is the good signal to be used for GPIF and SLAVEFIFO onto FPGA side ? Right ?
Yes, IFCLK is the right signal to use.
Onto the CPLD, CLK is there perhaps to synchronized some DATA coming from FX2LP18 … CLK_OUT can do the same ? CLKOUT and IFCLK are synchronous ?
No they are not synchronous.
Please use the IFCLK to synchronize data transfers with the CPLD.
You can use CLKOUT only to clock the peripherals, if you need to interface them with FX2LP for synchronous data transfers, then IFCLK should be used.
Thanks,
Yatheesh
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Ok. Good.
Remember my first question : Is the FX2LP18 IFCLK drive is enough to feed 3 inputs (CMOS inputs).
Or it is preferable to bufferize the IFCLK outputs (with minimal skews) BEFORE going to the FPGA or CPLD.
Regards.
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Hello,
We have not characterized this data. So I cannot guarantee you the proper functionality as individual current ratings and configuration of the device IO pins needs to considered.
Also, if 3 devices are connected to FX2LP18 for GPIF/Slave FIFO mode operation, FX2LP18 can only interact with one device at a time while the other 2 devices interface pins should be idle.
In this condition, if the other 2 devices CLK input pin is tri-stated/high impedance, the IFCLK can be connected to these devices.
Thanks,
Yatheesh