Cascaded flip flops out of phase?

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Pava_1191361
Level 3
Level 3
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I need a number of frequencies that are in phase, based on a clock frequency. In Psoc-6 this should be possible by simply cascading a number of toggle Flip Flops:

When simulated the signals are (as expected) in synch, as the output of one flip flop acts as source for the other flip flop:

pastedImage_2.png

However, when I measured the output on pin P1_2, P1_3 and P1_4, the output is NOT is synchronized:

pastedImage_0.png

It almost seems that P1_3 is triggered on the negative edge, in stead of the positive one, and P1_4 displays an unexpected phase shift related to P1_3. I had the same experience using D-Flipflops.

What is happening, and what can be done to synchronize these signals?

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Hi ,

thanks for looking into this. However, Ganesh put me on the right track, referring me to The Clock Synchronization and Routed Clock Implementation https://www.cypress.com/file/185351/download, and page 24 gave me the solution. Apparently the q output signal from the flip flop is synchronized with the provided clock signal, which means that each result is being offset with 1 clock cycle of the driving clock. The simplest solution is to tag each q result as asynchronous, using the UDB clock enable:

pastedImage_0.png

Just make sure the ClockOutSync setting is unchecked to indicate that the signal is asynchronous.

pastedImage_2.png

The datasheet of the Toggle Flip flop does not make any mentioning of this. The output now looks as expected. Only when zooming in, a delay of about 4ns between rising flanks (between each signal) could be detected, which is within spec.

pastedImage_3.png

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VenkataD_41
Moderator
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750 replies posted 500 replies posted 250 solutions authored

Hi Pava,

The Clock Synchronization and Routed Clock Implementation sections in page number 20 of the PSoC 4 System reference guide(link given below) might help you. Please go through it.

https://www.cypress.com/file/185351/download

Thanks

Ganesh

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
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Hi,

I tried with CY8CKIT-062-BLE.

Although this seems to be a little bit stupid, the phase seems to be reasonable.

Yellow is div2 (Pin_1), Red is dev8 signal (Pin_2).

IMG_4503.JPG

schematic

001-schematic.JPG

pins

002-pins.JPG

moto

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Hi ,

thanks for looking into this. However, Ganesh put me on the right track, referring me to The Clock Synchronization and Routed Clock Implementation https://www.cypress.com/file/185351/download, and page 24 gave me the solution. Apparently the q output signal from the flip flop is synchronized with the provided clock signal, which means that each result is being offset with 1 clock cycle of the driving clock. The simplest solution is to tag each q result as asynchronous, using the UDB clock enable:

pastedImage_0.png

Just make sure the ClockOutSync setting is unchecked to indicate that the signal is asynchronous.

pastedImage_2.png

The datasheet of the Toggle Flip flop does not make any mentioning of this. The output now looks as expected. Only when zooming in, a delay of about 4ns between rising flanks (between each signal) could be detected, which is within spec.

pastedImage_3.png

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Kenshow
Level 8
Level 8
Distributor - Marubun (Japan)
50 solutions authored 25 solutions authored 10 solutions authored

Hi,

The problem of routed clock distribution is solved by using PWM or timer output on the Tff input (T) instead of using the clock directly.

1.png

Regards,

Kenshow

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Kenshow
Level 8
Level 8
Distributor - Marubun (Japan)
50 solutions authored 25 solutions authored 10 solutions authored

Hi,

Why don't you use down counter in Utility component?

Refer to Let's make the dice of seven eyes on PSoC 6 with CapSense & sound,version 2​.

Regards,

Kenshow