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1 MHz adjustable output wave is probably outside of the PSoC realm. Typically, somewhat decent output can be obtained up to 100kHz.
To have arbitrary waveform at 1MHz needs ~100MHz sampling rate, so only hardware approach can work. Also analog chain must have >100MHz bandwidth. This job is typically for FPGA. It may be more reasonable for that purpose to buy off-the-shelf signal generator, like FY6900 (~$100). FPGA+DAC+Opamp alone will cost more than that.
If you can give more hints about the use of the ramp generator, then maybe we can suggest some analog solution using PSoC5. But building signal generator with such specs is no go.
Hi BoTa, Thanks for the quick feedback last night.
The application is a high current DC electronic load which we utilize in our labs to validate load transient response of our voltage regulators. Setup example below. We control a function generator and oscilloscope via Python scripts. The function generator provides a trapezoid waveform into the electronic load to control load slew rate and load magnitude. The oscilloscope provides feedback to Python for initial calibration of the function generator voltage levels for the proper DC loads and also monitors the load slew rate to correct function generator slew rates. The function generator output is ~100mV to 400mV with 500ns to ~50ns slew rates with frequency from 100Hz up to 1MHz...
We have a need for 100's of these setups and need to keep the solution portable. The loads are somewhat "disposable" after several soldering/desoldering events. Thus we are interested in adding a PSoC type device to our load boards and replace the function generator and scope. We understand there will be tradeoffs compared to high performance lab setups and need to understand the limitations. Customers utilize these loads and can help promote PSoC into new markets.
I have seen several of your responses on various ways to manipulate amplitudes with digital multipliers but then we need a DAC to get back to analog… I have wavedac8 with idac 2.4mA mode running at 500kHz but I do not have slew capability with only 4 bits, while I have the DDS24 ramp example modified to 1MHz with a clean ramp and paired square wave, but can’t seem to modify amplitude or slew rate of the square wave.
One thought, is it possible to adjust the pull-up voltage of an internal square to achieve amplitude modulation? Perhaps an IO pin were we can vary the voltage? We could then follow with an opamp to control output slew rate and offset.
Worst case, a more analogy concept is to use PSoC to create adjustable DC bias voltages used to bias an external inverter stage VDD and VSS. The resulting amplitude modulated square wave could then be fed into an opamp with slew rate adjustments…
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Thank you for describing the project. If the rise/fall slew rates are about the same, I believe this can be achieved using PSoC. The Cypress engineers are very knowledgeable about this product. The ramp/fall rate can be controlled with external slew rate limiter (some trans-conductance Opamps may work well for this purpose).
I recommend to try DDS32 component for generating base frequency. It is somewhat similar to DDS24, but, unlike it, the DDS32 is build entirely in UDB Datapath. It has less features, but can operate at higher frequency (>80 MHz) and greater resolution (up to 32-bit).
Attached is DDS32 library (v0_2), and DDS32 overclocking demo project. Some other project can be found here:
The (optional) rotary encoder with a button switch was used in this project to control the output frequency. Corresponding QuadDecoder_SW library can be found here
P.S. I caught the last Gordon Conference at Rhode Island when they were serving a beer (with lobsters)!
Attached another demo project showing varying amplitude of the digital output by using special pins feature Vref. The SIO pin is configured to be powered from internal buffer controlled by Vref. The output digital pulse amplitude can be varied from 0.5V to 4.1V by varying Vref voltage. The slew rate does not seem to be affected by output amplitude.
Using Vddio is another way achieving same result, but I can't demo it using KIT-059 as it seems to be hardwired.
Optional Pins Annotation Component, helping Pins configuration can be found here:
Attached is project archive, using DDS32 and QuadDecoder_SW libraries from above.
Figure 1. Project schematic using SIO Pin_120 Vref feature to control digital output.
Figure 2. SIO Pin_120 internal configuration using Vref feature to control output amplitude.
Figure 3. DDS at 1kHz, Vref = 4.1V. Yellow trace - VDAC, blue trace - DDS output.
Figure 4. DDS at 1kHz, Vref = 2.1V. Yellow trace - VDAC, blue trace - DDS output.
Figure 5. DDS at 1kHz, Vref = 0.5V. Yellow trace - VDAC, blue trace - DDS output.
Figure 6. DDS at 1MHz output, Vref = 4.1V. Yellow trace - VDAC, blue trace - DDS output. DDS trace (blue) is using 100x (uncalibrated) probe. Scope BW is 60MHz.
Thank-you Odissey1 for both suggestions. We will try this week. Danny
Attached below are two projects using custom component for digital control of the clock slew rate (SLR10). It is a 10-bit DDS, which is being reset on each rising/falling edge of the modulation (carrier) clock. It is similar to the DDS24 component it terms that it is build using only PLD space of the PSoC5. It operates up to 58MHz of BUS_CLK but could be overclocked up to 80MHz at room temperature.
The projects provided are the same except than one is using a rotary encoder for updating parameters, and another utilizes simple sweep timer.
Both projects use custom-made R2R DAC to convert digital bus from the SLR10 into the analog output signal. There are some imperfections due to poor timing of the bits and capacitive load of the protoboard. Using real DAC with parallel input (like DAC902) should give better performance. Please inspect the scope screenshots. I will upload a video later. Note that scope bandwidth and quality of the probe are greatly affecting shape of the high-speed traces.
Video of the project:
The SLR10 library is attached. The datasheet is not available for this draft version, but DDS24 datasheet can be used as a reference.
Project also uses external libraries:
PSoC Annontation Library: PSoC Annotation Library v1.0
Figure 1. Project schematic. Modifying slew rate and amplitude using SLR10 and external R2R DAC on SIO pins. Load resistor R_1 reduces output amplitude down to approx. 600mV and shortens o-scope rise time to about 50ns.
Figure 2. DDS32 provides modulation (carrier) clock for SLR10. Note that it is set to operate in 24-bit mode to (slightly) improve timing.
Figure 3. Project annotation using PSoC Annotation Library. Note the selection of the SIO pins to provide uniform digital signals on bits 0 to 3. Other SIO pins (I2C, UART) have traces attached to the KitProg, greatly affecting digital pulse shapes.
Figure 4. Blue trace - 100kHz carrier clock from DDS32. Yellow - R2R DAC output. The slew rate is set to 1.16MHz.
Figure 5. Blue trace - 1MHz carrier clock from DDS32. Yellow - R2R DAC output. The slew rate is set to max (26MHz). Note that observed traces are greatly affected by the o-scope bandwidth, quality of the probe and parasitic capacitances of the protoboard. Here: scope bandwidth is 60MHz (RIGOL DS1054z), probe Tek 200MHz 1:10 (yellow trace), and custom-made 1:100 5k resistive probe (blue).
Figure 6. Blue trace - 1MHz carrier clock. Yellow - R2R DAC output. The slew rate is set to (2 MHz)
Figure 7. Blue trace - 1MHz carrier clock. Yellow - R2R DAC output. The slew rate is set to 11.6MHz. VDAC amplitude is 255.
Figure 8. Same as Figure 7, but the VDAC amplitude is 40.