Clock_1_SetFracDivider only allowing 16 bits when it says it allows 24 bits

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KyWe_1936431
Level 2
Level 2
Welcome!

Hello,

I am using a clock divider to control a DMA sine wave and if I set the divider above 65536 it doesn't work. In the description of Clock_1_SetFracDivider it says the clock divider can be up to 16777216.

Thank you,

Kyle

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1 Solution

Kyle,

I have SOME answers for you.

You were correct.  The way you had it configured the clock divider being used was assumed to be 16.5-bit.   This was because your target output frequency was 500KHz.  (=3000KHz/6)   Therefore the Application Build "Assumed" you only needed the 165-bit divider.

Wrong assumption. 

I made two changes to your program:

  • I upped the Clk_Peri to 24MHz.
  • I changed Clock_1 configuration from Frequency: 500KHz  to Divider: 70000.   Since 70000 > 65535 this forced the Application Build to assign the 24.5-bit divider.

pastedImage_4.png

Once I set the var uint32_t Clk_Divide = 16777216-1;

I can achieve about 14mHz.   Note:  At this low frequency the VDAC has noticeable plateaus (steps).  At the lower frequencies you might want to use ALL of the 12bits allowed by the VDAC.

Len

Len
"Engineering is an Art. The Art of Compromise."

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10 Replies
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Kyle,

Which are you trying to control the fractional divider?   The PLL or the FLL?

Len

Len
"Engineering is an Art. The Art of Compromise."
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Hi Len,

The FLL leads to the peripheral clock in my system. There is a "new" clock called clock 1 that should be able to be divided.

Kyle

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Kyle,

Can you share your project with the forum?   If not, at least a minimized version?

Are you using Creator or ModusToolbox as the IDE?  My guess is you're using Creator.

There is some confusion on my part.

On the PSoC6, here is the count of peripheral clock dividers available to you :

  • 8 8-bit.
  • 16 16-bit
  • 4 16.5-bit (fractional)
  • 1 24.5-bit (fractional)

Is it possible you are already using the one 24.5-bit divider somewhere else in the design?

Len

Len
"Engineering is an Art. The Art of Compromise."
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Len,

I'm using creator yes. I'm not really a programmer so my code is probably confusing but I can attach if you think it will help. I am using m4 with the real time clock (RTC) and m0 with the MCWDT. An alarm every 3 seconds increases the frequency in m4. I am trying to figure out a system to reach several frequencies between 100 mHz to 10kHz

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Also is there a place in creator to check what dividers are available and which are in use?

Thank you,

Kyle

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Kyle,

I couldn't find anything to detail which clock divider resource was being used.

Len

Len
"Engineering is an Art. The Art of Compromise."
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Kyle,

I downloaded your project.   No compile errors.

I need to be able to run it correctly.  Other than loading it "as is" into a CYPROTO-063-BLE module, is there anything special I need to do?

I found the Clk_Divide variable.  Currently set to 48.  Based on your original post, I can increase this value to 65536 and it still works.  However, if I increase it more (say to 65537) it doesn't work.  Is this correct?

Assumption:  A higher value provides a lower Sine frequency.

Len

Update:  Measuring P9.6 (VDAC_Out_P9_6) I get a sine wave that starts at 617Hz and reduces by about 5 Hz every 2 secs until 299 Hz is reached.

Len
"Engineering is an Art. The Art of Compromise."
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Kyle,

I have SOME answers for you.

You were correct.  The way you had it configured the clock divider being used was assumed to be 16.5-bit.   This was because your target output frequency was 500KHz.  (=3000KHz/6)   Therefore the Application Build "Assumed" you only needed the 165-bit divider.

Wrong assumption. 

I made two changes to your program:

  • I upped the Clk_Peri to 24MHz.
  • I changed Clock_1 configuration from Frequency: 500KHz  to Divider: 70000.   Since 70000 > 65535 this forced the Application Build to assign the 24.5-bit divider.

pastedImage_4.png

Once I set the var uint32_t Clk_Divide = 16777216-1;

I can achieve about 14mHz.   Note:  At this low frequency the VDAC has noticeable plateaus (steps).  At the lower frequencies you might want to use ALL of the 12bits allowed by the VDAC.

Len

Len
"Engineering is an Art. The Art of Compromise."
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Len,

Thank you for working on this so much, and sorry I couldn't get back to you in time. I tried the divider set up and it worked perfectly. Thank you a lot. I am probably going to increase resolution like you suggested, but I have to get all the systems working before I worry about that. Thanks again and have a great day.

Kyle

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Kyle,

You're welcome.  I'm glad this solved it.   I appreciate your patience.   Sometimes the issue is a bit more complicated.

Len

Len
"Engineering is an Art. The Art of Compromise."
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