configure cx3 with ov7251

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bbfe_4086196
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Hi,

My case is ov7251 output 640*480 30fps raw10 to cx3 with 800Mbps mipi clock, one lane.

the current cx3 receiver configuration is like below:

cx3_receiver.jpg

From the red mark, there is a mismatch between ov7251 H-Active with cx3, i tried to fix it , but can't find a proper configuration for it.

The Vsync:

vsync.jpg

The Hsync:

hsync.jpg

period.jpg

The hsync period is 19.333us , same to cx3 receiver configure tool. but the H-Active is about 6.3us, near to 6.67us counted by tool.

should i must to configure it 4 us to match ov7251 H-Active?

based on above configuration, i test it on pc with eCAM, but no streaming data.

in the cx3 log, got some error 0x47

CyU3PDmaMultiChannelCommitBuffer Err = 0x47, size 16380

err  frmErrCnt: 255

      crcErrCnt:0

      mdlErrCnt: 0

      ctlErrCnt:  255

      eidErrCnt: 0

      recrErrCnt: 0

      unrcErrCnt: 0

      recSyncErrCnt: 0

      unrSyncErrCnt:  255

except H-Active, the pclk, hsync, vsync is correct ?

Also add CyU3PMipicsiSetPhyTimeDelay(0, 14); before CyU3PMipicsiWakeup(),

but the hsync seems to be incorrect. so, i removed it.

Any kind of help would be appreciate.

Thanks .

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1 Solution
Hemanth
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Hi

cx3-new.jpg

This configuration is correct. Please make sure Image sensor is also configured to output 480MHz MIPI Clock.

should i connect lane 2/3/4 data lane to GND?

If you are using CYUSB3065 part, then you should ground the unused data lanes. If you are using CYUSB3064 then only two data lanes are available and the others should be left open.

Regards,

Hemanth

Hemanth

View solution in original post

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6 Replies
Hemanth
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First like given First question asked 750 replies posted

The hsync period is 19.333us , same to cx3 receiver configure tool. but the H-Active is about 6.3us, near to 6.67us counted by tool.

should i must to configure it 4 us to match ov7251 H-Active?

The H-active values in the MIPI CSI-2 Inputs column and MIPI interface configuration column need not match.

except H-Active, the pclk, hsync, vsync is correct ?

Vsync and hsync periods looks okay.

Please reduce the MIPI clock to below 500MHz; Update the same in the configuration tool; Make sure that there are no errors for the new configuration and then test it.

Regards,

Hemanth

Hemanth
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Hi HemanthR_06

Thans for quick response.

I changed sensor's mipi clock to 480Mbps, leave cx3 receiver configuration no changes. like below

cx3_480.png

But, after that, the HSync is not correct. both period and H-Active is incorrect.

I want to know , should i change cx3's receiver configuration to match sensor's 480Mbps mipi clock or not?

if yes, please point me the direction to go, thanks.

or, continue to update sensor's register to fix HSync?

Thanks.

Vsync - 480Mbps mipi clock

vsync-1.jpg

HSync - 480Mbps mipi clock

hsync-1.jpg

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Hi HemanthR_06,

I move back to 800Mbps mipi clock, with following cx3 receiver configuration. the vsync/hsync period same to first post.

cx3-new.jpg

Add debug message at a debug thread (print error count every 1s), got following log:

from MIPI-CSI Protocol and Physical Layer Errors in CX3 (CYUSB3065 and CYUSB3064) – KBA228482

it's explained "

ctlErrCnt (Control Error (Incorrect Line State Sequence) Count)

This counter is incremented when escape mode is exited using the wrong sequence.

"

Question: Can we leave the unused MIPI CSI-2 data lanes of CX3 floating?

Answer: No. The unused MIPI CSI-2 data lanes of CX3 must be connected to ground. For example, if you use an image sensor with one MIPI CSI-2 lane, you should connect the second, third, and fourth MIPI CSI-2 data lanes of the CX3 to Ground.

My board data lane 2/3/4 is connected to the sensor, but actually the video data just only output to lane1 (use one lane).

should i connect lane 2/3/4 data lane to GND?

does ctlErrCnt  has releationship with hardware mipi connection ?

thanks.

Enter suspend                                                            --------------------> Firmware init done.

Completed 0 frames and 1 buffers. count 0 0

g_timer1 0, g_timer2 0

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 3

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 0 0

g_timer1 0, g_timer2 0

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 0

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 0 0

g_timer1 0, g_timer2 0

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 0

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 0 0

g_timer1 0, g_timer2 0

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 0

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 0 0

g_timer1 0, g_timer2 0

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 0

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 0 0

g_timer1 0, g_timer2 0

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 0

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Set Probe       1

Set Commit 1

esSetCameraResolution 1

set high speed vga 30fps

ov7251 power up

reg 0x100 val 0x1

UVC Started                                                                                      ----------------------------------> Start eCAM on PC

Completed 1 frames and 1 buffers. count 16368 3268

g_timer1 0, g_timer2 32

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 17                                                                                     -----------------------------------> ctlErrCnt increasing ....

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 16368 3268

g_timer1 0, g_timer2 32

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 76

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 16368 3268

g_timer1 0, g_timer2 32

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 135

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 16368 3268

g_timer1 0, g_timer2 32

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 193

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 16368 3268

g_timer1 0, g_timer2 32

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 251

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 16368 3268

g_timer1 0, g_timer2 32

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 255                                                                                 -----------------------------------> ctlErrCnt increase to 255, and stay there.

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

Completed 0 frames and 1 buffers. count 16368 3268

g_timer1 0, g_timer2 32

err frmErrCnt 0

crcErrCnt 0

mdlErrCnt 0

ctlErrCnt 255

eidErrCnt 0

recrErrCnt 0

unrcErrCnt 0

recSyncErrCnt 0

unrSyncErrCnt 0

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Hemanth
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First like given First question asked 750 replies posted

Hi

cx3-new.jpg

This configuration is correct. Please make sure Image sensor is also configured to output 480MHz MIPI Clock.

should i connect lane 2/3/4 data lane to GND?

If you are using CYUSB3065 part, then you should ground the unused data lanes. If you are using CYUSB3064 then only two data lanes are available and the others should be left open.

Regards,

Hemanth

Hemanth
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HemanthR_06 撰写:

Hi

cx3-new.jpg

This configuration is correct. Please make sure Image sensor is also configured to output 480MHz MIPI Clock.

Ok, I will try to monitor mipi clk+/-

should i connect lane 2/3/4 data lane to GND?

If you are using CYUSB3065 part, then you should ground the unused data lanes. If you are using CYUSB3064 then only one data lane is available and the other should be left open.

Yes, I use the cyusb3065-bzx , i will try to place other lane to ground.

cyusb3064 has two data lane, right ?

Regards,

Hemanth

Best regards,

dillon,

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Hemanth
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First like given First question asked 750 replies posted

Hi Dillon,

Yes. It was a mistake in my previous post (I have edited it now).

CYUSB3064 has 2 data lanes not 1.

Regards,

Hemanth

Hemanth
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