Cypress Streaming Example With an External Clock.

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raus_1269711
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In the attached streaming  example provided by Cypress, if I  change the firm ware for an external clock, it stops working.

Here is the code;

void TD_Init(void)             // Called once at startup

{

   int i,j;

CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation

                            // CLKOE=1, drive CLKOUT

   SYNCDELAY;

   // set the slave FIFO interface to 48MHz

   IFCONFIG |= 0x40;

   SYNCDELAY;

    // Default interface uses endpoint 2, zero the valid bit on all others

    // Just using endpoint 2, zero the valid bit on all others

    EP1OUTCFG = (EP1OUTCFG & 0x7F);

SYNCDELAY;

EP1INCFG = (EP1INCFG & 0x7F);

SYNCDELAY;

EP4CFG = (EP4CFG & 0x7F);

SYNCDELAY;

EP6CFG = (EP6CFG & 0x7F);

SYNCDELAY;

EP8CFG = (EP8CFG & 0x7F);

SYNCDELAY;

    EP2CFG = 0xE0;  // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x

   // We want to get SOF interrupts

   USBIE |= bmSOF;

  

   mycount = 0;

   // Prepare data

   for (i=1;i<5;i++)

   {

      EP2FIFOBUF[0] = LSB(mycount);

      EP2FIFOBUF[1] = MSB(mycount);

      EP2FIFOBUF[2] = USBFRAMEL;

      EP2FIFOBUF[3] = USBFRAMEH;

      EP2FIFOBUF[4] = MICROFRAME;

      for (j=5;j<1024;j++)

      {

         EP2FIFOBUF = i;

      }

      EP2BCH = 0x02;

      EP2BCL = 0x00;

   }

    Rwuen = TRUE;                 // Enable remote-wakeup

////////////////////////////////////////////////////////////////////////////////////////////////////////// The following two lines is what I add./////////////////////////////////////////////

IFCONFIG = 0x43; // Slave FIFO mode of FX2LP

SYNCDELAY;

}

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1 Solution

When using GPIF master mode or Slave FIFO mode in FX2LP, if the interface does not work for lower frequencies (IFCLK below 10MHz), It is advised to lower the CPU clock frequency to 12 MHz or 24 MHz using the CPUCS register (CLKSPD[1:0]).

Thanks,

Yatheesh

View solution in original post

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9 Replies
YatheeshD_36
Moderator
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750 replies posted 500 replies posted 250 solutions authored

Hello,

When you change the IFCONFIG register's IFCLKSRC bit to select external clock, the firmware expects the an external clock to to supplied on the IFCLK pin for the operation. Please let me know if you are supplying a external clock on the IFCLK pin?

Thanks,

Yatheesh

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Hello,

I supply a 12 MHz external clock.

The problem I have is with an internal clock I get the right codes, but not with an external clock.

Thanks,

Ray

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Hello,

Please make IFCLKSRC=0 by setting IFCONFIG = 0x03 instead of IFCONFIG |= 0x40 to select external clock.

i.e. IFCONFIG = 00000011  // external clock, synchronous slave FIFO mode.

Also when using external clock, the external clock should be present before the IFCLKSRC bit of IFCONFIG register is set to 0.

Please make sure that the above condition is met.

Thanks,

Yatheesh

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Hello,

following two lines is what I add./////////////////////////////////////////////

IFCONFIG = 0x43; // Slave FIFO mode of FX2LP

SYNCDELAY;

Is this wrong?

I did change it  to

IFCONFIG = 0x03;

with still the same issue.

Thanks,

Ray

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Hello Ray,

Can you please confirm if the external clock is present on IFCLK before the firmware is executed or atleast before the TD_init () is executed?

Thanks,

Yatheesh

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The external clock is present.

It is actually the clock output of the FX2 divided by 8.

That is a 6 MHz clock.

If I divide it b2 4,ie 12 MHz, all is fine.

The problem is with the 6 MHz clock.

Thanks,

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Hello,

Can you please share the .c file.

Thanks,

Yatheesh

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Hello There,

I have emailed it to you.

Thanks,

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When using GPIF master mode or Slave FIFO mode in FX2LP, if the interface does not work for lower frequencies (IFCLK below 10MHz), It is advised to lower the CPU clock frequency to 12 MHz or 24 MHz using the CPUCS register (CLKSPD[1:0]).

Thanks,

Yatheesh

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