- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I'm trying to achieve the following:
One component in my design outputs a trigger signal. On each positive edge of this output, I'd like use one DMA channel to do the following things:
- Transfer one halfword from the SAR ADC to a 16-bit UDB
- Transfer one word from a timer to a memory location (uint32_t)
- when both are done, the DMA channel should generate one output trigger that is routed into the UDB.
I connected the DMA channel's trigger input and output to a scope. I can see the input triggers, but the output is silent. These are my descriptors:
My guess is that, since descr_timer is chained back to descr_adc, an endless loop is created and no trigger is generated because the entire (endless) chain is never completed. However, I've tried many other combinations of settings and none of them had the desired result.
I've also attached the current state of the whole project (the DMA component in question is in the top level design).
I'm thinking about handling DMA errors with the DMA's interrupt. It would be triggered only on errors, not on channel completion. Any advice on this is appreciated, but not the main point of this question.
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ChRe_4711096 ,
To answer your initial question about "cascading the DMAs" please find the attached project in which I have cascaded two DMA components. The input trigger to the first DMA (DMA_1) is given using the TCPWM based counter.
Please check if it is working at your side and update me.
Thanks
Ganesh
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Christoph,
One doubt regarding the design, why the descriptors are chained to each other ? How often the trigger signal (EOS out) is generated?
Best Regards,
Vasanth
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The descriptors are chained because they transfer both a timestamp and an ADC sample. Two of these tuples are used to calculate the time at which the ADC input crossed zero. EOS out is triggered at roughly 360 90 kHz, and I might try to double that to 720 180 kHz. (Sorry for the previous values - they were the sum for 4 ESC components)
I've attached an 8-bit demo of the UDB I'll use to extract the ADC sample sign and generate separate triggers based on that. It also allows to set a threshold around zero, for blanking out noise.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ChRe_4711096 ,
To answer your initial question about "cascading the DMAs" please find the attached project in which I have cascaded two DMA components. The input trigger to the first DMA (DMA_1) is given using the TCPWM based counter.
Please check if it is working at your side and update me.
Thanks
Ganesh