gpio power up

[ETRO_SSN583]

I read/hear conflicting information on GPIO state during power up.

I read in some docs that GPIO are configed as inputs during power up.

Then in other I read that the GPIO pin tracks its Vddio supply until 1.45 V,

then takes on NVL latch settings. This tells me if a pin drives a bipolar,

which in turn drives a relay, that during power up the relay will glitch on until

NVL state is acquired. That in turn tells me do not use a bipolar because of

its Vbe threshold of ~ .7V, rather use a MOSFET because its Vth is >> 1.45 V

(typically).

I would appreciate clarification on this.

Regards, Dana.

[ETRO_SSN583]

Here is out of PSOC 4 ap note -

3.3 Startup and Low-Power Behavior On reset/power-up, all GPIO pins start up in the high-impedance analog mode, that is, with the input buffer and output driver disabled. These GPIO pins remain in this mode until the reset is released; then the initial operating configuration of the associated registers of each GPIO pin is loaded during boot and takes effect at that time. During run time, GPIOs can be configured by writing to the associated registers.

Out of a ap note for PSOC 5LP GPIO -

2.6 Startup and Low-Power Behavior Out of the box, all GPIO pins start up in an Analog HI-Z state, where they remain until reset is released. The initial operating configuration of each pin is loaded during boot and takes effect at that time. You can change the reset behavior of GPIOs us

The above seems misleading, in that first blush one thinks they are in HiZ thruout ramp. But then "until reset is released", so what is the active

range of reset pin ? Then it further confuses because of the "boot time" only then is pin behavior controlled. UGH !

Here is out of PSOC 5LP datasheet -

11.4 Inputs and Outputs
Specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. Unless otherwise specified, all charts and graphs show typical values.
When the power supplies ramp up, there are low-impedance connections between each GPIO pin and its VDDIO supply. This causes
the pin voltages to track VDDIO until both VDDIO and VDDA reach the IPOR voltage, which can be as high as 1.45 V. At that point, the
low-impedance connections no longer exist and the pins change to their normal NVL settings.
Also, if VDDA is less than VDDIO, a low-impedance path may exist between a GPIO and VDDA, causing the GPIO to track VDDA until
VDDA becomes greater than or equal to VDDIO.

So above says not HiZ until 1.45V .....

Regards, Dana.

[ETRO_SSN583]

So we should NOT recommend a Bipolar to drive a load, like an NPN, rather should be a MOSFET with at

least a Vth > 1.45 volts, is that correct ? Like driving speakers, relays, leds.....Unfortunately most MOSFETS

do not spec best case turn on......

So that PSOC does not false turn on a load during startup.

This could be a major safety issue depending on design. Cypress needs to update ap notes

and blogs on this.

Regards, Dana.

[Len_CONSULTRON · Accepted solution]

Dana,

Let's see if I can be of any help.

Be careful.   If the issue you have is with power up, the ramp-up voltages are very unpredictable due to:

• The power source impedance feedback regulation characteristics
• Parallel capacitance
• Series resistance
• Series inductance.
• Transient loading of VDDD
• Transient loading of VDDA
• Transient loading of VDDIO

If you are worried about a non-power up reset, there are things that can be done to control the effects on GPIO.

It would be of help if you can draw your circuit that you are trying to control.  If you have so already, you can use TopDesign schematic entry to draw this out with the external circuit elements.

If you can then share with circuit with the forum, myself and others might be able to suggest how to prevent glitching.

Len