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Yes, the system clocking is fixed at 403.2 or 384 MHz for 19.2 MHz crystal, which is configured using the setSysClk400 parameter in the CyU3PSysClockConﬁg_t structure passed to the CyU3PDeviceInit call.
The GCTL_PLL_CFG register holds the information about the PLL configuration.
We do not recommend increasing the PLL clk output for 19.2 MHz. If you need higher frequency system clock, you can use the 26-MHz or 52-MHz input clock. Please refer to Section 220.127.116.11 CPU Operating Frequency from the FX3 TRM.