BCM20737S layout footprint

[huangj]

Hi everyone,

The following picture is our PCB layout footprint. We use the footprint to make our test board. But we have some trouble, our success rate of soldering  is only 60%. Even we use the stencil, the success rate of soldering is still low. Our hardware team think the problem is in the soldering(4 GND Pad-45~48 is float). So they would like to change BCM20737S layout footprint. The hardware team would like combine 4 GND pad(45~48) into a GND pad. Will it affect the performance of the antenna?

[MichaelF_56]

We will need to check with our packaging house to see if this is this is ok.

[BoonT_56]

From whom are you getting your SIP module? This vendor should be in a better position to advise.

[MichaelF_56]

I checked and this should not be an issue.

[Anonymous]

Have a look at Broadcom's reference designs:

iBeacon:

iBeacon BCM20737S Reference Design PDF Schematic (Module)

iBeacon BCM20737S Reference Design Gerber Files (Module)

iBeacon BCM20737S Reference Design Allegro Layout File (Module)

Wiced Sense 2

WICED Sense 2 Schematic Files

WICED Sense 2 PCB Files

or, the most important bit for you as a screenshot of the top layer of the iBeacon PCB:

(soldermask as well as stencil only had the smaller individual openings as in you first image, not a big open ground pad!)

Oliver

[Anonymous · Accepted solution]

  Hello Huangj,

  What is missing from your image is the Soldermask for your pins along with what ends up happening on your PCB design if you have a GND Pour on Layer1 as to how this affects the GND pins that are on the Module.  I have developed numerous different PCB's based on the BCM20736S, BCM20737S, and earlier on the BCM20732S and I have had nearly 100% success.  The ultimate affect of a GND pour on Layer1, Vias and Via Sizes used underneath the package, and defined Soldermask all are extremely important in how well any sort of QFN/LGA package will adhere to a PCB. 

As an example I have shown a screenshot of our newest EMRF-20737S-TH which is a Micro Breakout board for the BCM20737S with Pushbuttons, LED's, DC/DC, and a Slide switch to easily go between Debug/App and Programming mode...you will see that there is very minimal solder mask, 3mil around each pad and that the GND pour underneath the package is a 'Hatched' GND pour so as to allow a moderate thermal relief allowing the center pads to heat appropriately.

Also notice there are Minimal Vias used underneath the LGA package and in fact there is a 'DUMMY' via in the Upper Left hand corner to ensure the package sits flat, I.E. - There are Vias essentially in each corner underneath the package so it does not 'tombstone'.

Regards,

Frank

Embedded Masters

[huangj]

Hi Frank,

Thank you for comment. I will tell the result to my hardware team. We will reduce each pad size to 0.3 * 0.5(mm), and use new footprint to make stencil and test board.

boont​

Our vendor is Avnet. We check the issue from them, but the problem is very urgent. So I post the question to the community. I got the mail from Avnet FAE, and they give us some suggestion.

Regard,

Jack