The AN70707 recommends using ASEMB-19.200MHZ-LY-T (for 19.2 MHz clock).
You can use same company's 52 MHz clock oscillator provided the phase noise requirements, mentioned in Table 6, Section 5.1.2, Page no. 11 of AN70707, are fulfilled.
You can take a look at this thread as a reference for the phase noise requirement to be met: FX3 Oscillator Phase Noise
Unfortunately, we don't have any reference schematic or layout for such a design.
Also, as mentioned in the cyu3system.h file,
The SYS_CLK_PLL value is 416 MHz if the input clock frequency is 26 MHz or 52 MHz;
and it is 384 MHz if the input clock frequency is 19.2 MHz or 38.4 MHz. The
SYS_CLK_PLL frequency can be changed to 403.2 MHz from 384 MHz by passing appropriate
parameters to the CyU3PDeviceInit function.
- Using a 19.2MHz or 38.4MHz and setting the appropriate parameters in CyU3PDeviceInit function would still make the input clock frequency to be at 403.2 MHz (which makes the max GPIF II clock frequency as 100MHz (max)).
Are there ANY benefits to increasing the clock oscillator frequency?
The overall performance of the system would improve when a higher clock oscillator is used.
The PLL dividers will be adjusted based on 416MHz (instead of 403.2MHz, when using 19.2MHz or 38.4MHz) accordingly when using a 52MHz oscillator and there will be improvement in the corresponding DMA clocks, etc.