fx3 config xc7a50t slowly in slave selectMAP mode

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hola_4724651
Level 2
Level 2

it takes at least 90s to config fpga via fx3 in slave selectMAP mode , while the bitfile is about 8MB.

how can i reduce the time cost? where can i change config clock?

thanks。

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Hello,

Thank you for the confirmation.

As mentioned in the above thread that I was referring to, the performance limitation is because of the bit-banged GPIO's being used for SPI where the max frequency is in the order of ~500KHz.

Alternatively, instead of using bit-banged GPIO's to emulate a parallel data bus, you can develop a GPIF II state machine that can be used to configure the FPGA at much higher rates and in less amount of time (according to your query).

Regards,

Yashwant

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YashwantK_46
Moderator
Moderator
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100 solutions authored 50 solutions authored 50 likes received

Hello,

Please change the  i2cConfig.bitRate    = 100000; to  i2cConfig.bitRate    = 1000000;     //1MHz I2C bit rate

in the CyU3PI2cSetConfig() structure that is being passed to this API.


This will make the I2C Master block to work at a bitRate of 1MHz.

By default, the I2C master block is set to work at 100KHz.


Regards,

Yashwant

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i'm sorry but i use spi mode, not i2c.

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Hello,

The SPI maximum operational frequency in FX3 is 33 MHz.

The spiConfig.clock is used to set the max clock frequency of the SPI block.
Please let me know the value being passed to this parameter( .clock) in the CyU3PSpiSetConfig() config structure.


The max frequency that can be set as follows for 33MHz:

spiConfig.clock = 33000000;

Regards,

Yashwant

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sorry. but my question is about slave selectmap, not about spi/i2c.

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Hello,

A similar query is being handled on this thread: Accelerate the speed of GPIO emulated parrallel IO

Can you please let me know if you are using a similar approach?

If not, can you please elaborate more on your application so that I can understand it better?

Please share your firmware so that I can look into it to understand it better.


Regards,

Yashwant

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hola_4724651
Level 2
Level 2

thanks, it's almost same as that one, and we've finished the config work.

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Hello,

Thank you for the confirmation.

As mentioned in the above thread that I was referring to, the performance limitation is because of the bit-banged GPIO's being used for SPI where the max frequency is in the order of ~500KHz.

Alternatively, instead of using bit-banged GPIO's to emulate a parallel data bus, you can develop a GPIF II state machine that can be used to configure the FPGA at much higher rates and in less amount of time (according to your query).

Regards,

Yashwant

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