FX3 Slave FIFO Stream (GPIF Example 4)

[TaGr_401321]

I’ve been working through the examples in the book SuperSpeed Device Design by Example and would like to use the Slave FIFO example in Chapter 11 as the foundation for a project I’m working on. However, I’m having trouble with dropped data during the transfer and was hoping to get some insight/debug help. 

A bit of background on my hardware setup…I’m using the CYUSB3KIT-003 SuperSpeed Explorer Kit in conjunction with CYUSB3ACC-005 FMC Interconnect Board.  The FMC board is connected to a Xilinx ZC702 Evaluation Board.  So, there are some differences in regards to the hardware setup vs. the example given in the book where the CPLD accessory board is used. I am fairly certain that I’ve worked through all of the IO mapping accordingly because I do get the example to work, just not reliably.  The FX3 is loaded with firmware file ‘GPIF_Example4.img’...so DMA watermark value is set to 4.

When I run the example, I have a few main issues that are highlighted below:

1. There’s a bunch of sampled data in the form of 0xEFEFEFEF that is taken prior to the start of the counter data.  I have hardwired the ‘select’ input to be write-only for now as I’m only interested in streaming data from the FPGA to the FX3.  So 'Sel' in the attached code is '0'.
2. I have a repeating gap of 1 at indices that equate to exactly 4096, so I seem to be dropping exactly one 32-bit counter word during buffer swaps?  The FIRST time this occurs is at byte index 16384 (word index 4096), instead of getting 0x00001000, I get 0x00001001.  This index is after all of the 0xEF data was stripped out from the beginning of the collected data packet.
3. There’s also a repeating gap of -262208 at various indices, but I’m thinking that if I can solve the issue in #2 above I’ll have more insight here.

Under normal circumstances I could get in a lab and hook up a logic analyzer to gain more insight, but that’s not feasible for at least another couple of months.

I’ve also attached my VHDL code that I ported from the file ‘FifoMasterCounter.v’ included as part of the examples from the book.

Any ideas on where to start or go from here? 

[JayakrishnaT_76 · Accepted solution]

Hello,

Please share me the following details:

1. Please try reading the data using control center application from the BULK IN endpoint and check if you see the issue 2 with control center application also.

2. Please share the CollectData.bin file so that I can understand things better. If the file size is too large, then please share snapshots.

3. Please share snapshots of CheckData.exe.

4. Please confirm that reset input is initially HIGH and then made LOW.

5. Also did you program FX3 or FPGA first?

Also in order to debug the issues, can you please modify the following code

counter <= counter_i when (OE = '1') else (others => 'Z');

to

counter <= counter_i when (OE = '1') else (others => '0');

Please check if you are getting 0xEFEFEFEFs at the start after this or not.

Best Regards,

Jayakrishna