Attachments are accessible only for community members.
Jul 19, 2020
08:34 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 19, 2020
08:34 PM
Hi,
请教一个技术问题关于赛普拉斯 CY7C68013的问题,PCB Layout的时候如附件截图的数据总线和地址线需不需要做等长处理? 是否此款芯片只有USB2.0的DP&DN管控一下等长和阻抗?附件截图请参考,谢谢。
Solved! Go to Solution.
1 Solution
Jul 20, 2020
01:20 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 20, 2020
01:20 AM
2 Replies
Jul 20, 2020
01:20 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 20, 2020
01:20 AM
我们的要求里只有对DP DM要求阻抗匹配。这些IO信号没有等长的要求。
Jul 20, 2020
06:44 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 20, 2020
06:44 PM
您好,
非常感谢您的解答,谢谢。