AIRCR.PRIGROUP[2:0] value using FreeRTOS for PSoC6

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YoIs_1298666
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Hello,

What is the setting value of AIRCR.PRIGROUP[2:0] using FreeRTOS?

The result of reading the AIRCR register in the task was 0xFA050000.

AIRCR.PRIGROUP[2:0] =000 ?

   volatile uint32 temp32;

   ...

   temp32 = SCB->AIRCR;

The result of reading both NVIC_GetPriorityGrouping() and NVIC_GetPriority(SysTick_IRQn)was below.

        temp32 = NVIC_GetPriorityGrouping();

        temp32 = NVIC_GetPriority(SysTick_IRQn);

result:  NVIC_GetPriorityGrouping()=0

            NVIC_GetPriority(SysTick_IRQn)=7

Best regards,

Yocchi

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1 Solution
BragadeeshV
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hi YoIs_1298666​,

The Priority grouping for PSoC 6 is set to 0. This means that the group priorities and the sub priorities are set as the following:

pastedImage_2.png

In PSoC 6, the __NVIC_PRIO_BITS is set to 3. The implementations having fewer than 8-bits of interrupt priority treat the least significant bits as zero. This means that lower significant bytes less than 3 is set to 0. For PSoC 6, it will be something like below:

pastedImage_3.png

The default implementation in PSoC 6 is group 0 priority grouping. Therefore, it has 8 configurable group interrupt priority from 0 to 7 with no sub group priority.

References:

1. Cortex™ -M4 Devices : Generic user guide

2. Interrupt Priority Grouping in ARM Cortex-M NVIC

Regards,

Bragadeesh

Regards,
Bragadeesh

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2 Replies
BragadeeshV
Moderator
Moderator
Moderator
First question asked 1000 replies posted 750 replies posted

Hi YoIs_1298666​,

The Priority grouping for PSoC 6 is set to 0. This means that the group priorities and the sub priorities are set as the following:

pastedImage_2.png

In PSoC 6, the __NVIC_PRIO_BITS is set to 3. The implementations having fewer than 8-bits of interrupt priority treat the least significant bits as zero. This means that lower significant bytes less than 3 is set to 0. For PSoC 6, it will be something like below:

pastedImage_3.png

The default implementation in PSoC 6 is group 0 priority grouping. Therefore, it has 8 configurable group interrupt priority from 0 to 7 with no sub group priority.

References:

1. Cortex™ -M4 Devices : Generic user guide

2. Interrupt Priority Grouping in ARM Cortex-M NVIC

Regards,

Bragadeesh

Regards,
Bragadeesh
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Hello Bragadeesh-san,

I understand very well.

Thank you very much for your help.

Best regards,

Yocchi

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