PSoC Burning after few seconds

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ALDE_1053476
Level 3
Level 3
10 replies posted 10 questions asked 10 sign-ins

Hello,

I'm testing prototypes of the attached schematic.

Very Often The PSoc heats and gets broken after few seconds.

Any I dea on where the Issue can be?

Thanks,

Alfonso

Hi all,

thanks far all your feedbacks, I'm still fighting with the circuits, (they're winning for now)

Alfonso

Messaggio modificato da ALFONSO DESIDERIO

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1 Solution

here was a similar case with the board for 5LP - heating and destruction (not every time you turn it on).

It turned out that all the power circuits were carried out separately (VSSA, VSSD ...)

And I forgot to connect them on the board (VSSA + VSSD).

The chains were connected inside the crystal; heating and destruction occurred.

calling the circuit by the tester did not help - since there is a connection inside the crystal.

Just a visual check.

Evgeniy.

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6 Replies
BiBi_1928986
Level 7
Level 7
First comment on blog 500 replies posted 250 replies posted

A quick look at schematic shows 2 signals could be shorted together if R16 and R18 are mounted.  Check to see that these are not mounted.

The PSoC voltage and ground pin connections appear to be correct.  I've not checked the respective pin numbering.

If using Kitprog to program the PSoC, this could be an issue since it only operates at 5V, not 3.3V.  And, the Kitprog would attempt to supply power to the rest of the pcb circuitry.

If using a Miniprog, make sure it is set to 3.3V before attaching it.  Or, configure Miniprog to use target voltage source.

What's going on at U2?  The SPI signals are going to the wrong pins.  Check out the labels!

Also, check for solder shorts around PSoC chip.

Good luck with your project.

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

I agree with BiBi-san's opinions.

Especially about U2, if the voltage levels of U2's DO and MOSI is not same,

there  can be a lot of current going.

Although I hope that you have already done this,

in case you have not, I recommend you to download and check

AN88619 - PSoC 4 Hardware Design Considerations

https://www.cypress.com/documentation/application-notes/an88619-psoc-4-hardware-design-consideration...

Appendix C is "Schematic Checklist"

Double checking your circuit with the checklist will not harm.

Hoping that your project will be OK soon.

moto

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ALDE_1053476
Level 3
Level 3
10 replies posted 10 questions asked 10 sign-ins

Hi all, thanks for your feedback.

R18 and R16 are not mounted.

To program and debug PSoc I'm currently using a Kitprog modified (D1 removed) with a Piggy back board able to supply a set ov Voltages.

3V3 is currently selected (and it's signaled by a combination of Leds)

Yes I'd already seen the mess on U2. It was worked around by wiring the correct connections.

No short circuits have been detected watching board with the microscope.

I add some more information:

I assembled 2 prototypes of this circuit. In some cases they both have been working fine for hours.

The issue seems to appear while connecting / disconnecting Kitprog.

Any other ideas?

Thanks,

Alfonso

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

> Any other ideas?

Since I'm not a hardware engineer, following are "idea" and may not be helpful, but let me try my best.

(1) I wonder what is VBT and VBT_S?

    When I tried to find 18650, an amazon page showed that the voltage could be up to 4.2V.

    From the datasheet, GPIO abs max is VDD+0.5V, so depending on the voltage of the battery it can be too high.

(2) As you see that the problem tend to happen when KitProg is intact.

   I would check the VDD voltage with and without KitProg.

(3) Similarly I would check connection with PSoC and non-3.3V area,

Audio_En, Batt_chg, V_Mon as they seem to be connected to a device driven by higher voltage.

That's about all I can think of now...

moto

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As Moto pointed out, V_Mon and V_Mon_En are high voltages applied to PSoC GPIO pins.  GPIO input voltage should not exceed 3.3V in this design.  The higher voltage will forward bias the GPIO pin protection diodes and this will become the Vdd on the PSoC (minus a diode drop).

As a test, remove R25 and R30.  I know this could upset the software, but s/w is easily changed.

Also, this PSoC allows SWD port pins to be used as GPIO.  Check that PSoC has not been configured to use these pins as GPIO.  This could conflict with Kitprog signal direction.  This configuration is done through Creator, not through s/w.

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here was a similar case with the board for 5LP - heating and destruction (not every time you turn it on).

It turned out that all the power circuits were carried out separately (VSSA, VSSD ...)

And I forgot to connect them on the board (VSSA + VSSD).

The chains were connected inside the crystal; heating and destruction occurred.

calling the circuit by the tester did not help - since there is a connection inside the crystal.

Just a visual check.

Evgeniy.