Synchronize ADC_SAR

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JaOr_4642046
Level 3
Level 3
First like received

Hi to everyone and thanks in advance.

Here is my question.

As I can see in page 2 of  ADC_SAR reference sheet.

pastedImage_0.png

My question is,  how could I be sure that the signals are synchronized? I will try to explain myself.

I got this:

pastedImage_0.png

As can seen in the above image, I have an ADC_SAR it is controlled by a 1Khz (A)  input signal in "soc" and  in the ADC_SAR´s configuration I have a clock frequency of 1777.778. which gives me one isr_ADC (B) output signal each 1uS.

If I understood correctly, in the rising edge of the 1khz signal A) the ADC_SAR start to convert the input and after a few micro-seconds I got the B) (isr_ADC). and this happens JUST ONE TIME in each 1khz rising edge, doesn´t it?

my doubt is :

                         1)  the condition of :  "least one ADC_SAR clock cycle wide",       =====> it ok.

                         2) "This signal should be synchronized to the ADC_SAR clock"   =====> how could I be sure this is correct with the setting is shown above?  do I need to add something?

I saw a strange behavior in the isr_ADC output (using an oscilloscope), in the period of 1 ms (1 khz in A) ) time to time I could see two (or more) interrupts followed one another (at different distances) .

why can this happen?

this is more or less the idea.


I hope some of you can explain to me, how can I set the ADC correctly?.

Thank you very much for your time.

Regards.

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1 Solution
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

It was my bad, I missed that "1kHz" was input.

So I changed the 1kHz clock with an external Digital Input.

And I connected the input to the Oscilloscope's 1kHz calibration signal.

NOTE: For me there was no change in the result.

So I imagine that may be you had some bouncing in the clk in your original post.

Oscilloscope

IMG_4296.JPG

Schematic

010-schematic.JPG

Pins

011-pins.JPG

ADC configuration (not changed but just in case)

012-adc_config.JPG

main.c

================

#include "project.h"

volatile int adc_done_flag = 0 ;

CY_ISR(adc_done_isr)

{

    adc_done_flag = 1 ;

    ADC_Done_Write(1) ;

}

void init_hardware()

{

    CyGlobalIntEnable; /* Enable global interrupts. */

    isr_ADC_ClearPending() ;

    isr_ADC_StartEx(adc_done_isr) ;

   

    ADC_SAR_1_Start() ;

}

int main(void)

{

    init_hardware() ;

    for(;;)

    {

        if (adc_done_flag) {

            adc_done_flag = 0 ;

            CyDelayUs(1) ; /* 1us */

            ADC_Done_Write(0) ;

        }

    }

}

================

moto

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5 Replies
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Jaor,

The rising edge on the SOC just starts endless ADC conversions, nothing more.

For ADC synchronization you must either: (1) use external clock and calculate timing yourself, or (2) use a Sample Mode = Hardware Trigger.

/odissey1

Thanks BoTa,

But in this case, that means when I start the conversions with the rising edge of the 1 khz signal,

          a) do I have at the "eoc" output a train of pulses? I means, if the conversion is (for instance) about 1us, do I have 500 interrupts on                isr_ADC? (assuming just the positive cycle is the active)

Sorry I am a bit confused with this.

          b) In this case,  if I wish just one interruption each 1 ms, how can I do that?

Regards.

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

I have just tried the following with my CY8CKIT-059.

Schematic

001-Schematic.JPG

ADC Config

003-ADC_Config.JPG

Pins

002-pins.JPG

Oscilloscope waveform

IMG_4295.JPG

main.c

=====================

#include "project.h"

volatile int adc_done_flag = 0 ;

CY_ISR(adc_done_isr)

{

    adc_done_flag = 1 ;

    ADC_Done_Write(1) ;

}

void init_hardware()

{

    CyGlobalIntEnable; /* Enable global interrupts. */

    isr_ADC_ClearPending() ;

    isr_ADC_StartEx(adc_done_isr) ;

  

    ADC_SAR_1_Start() ;

}

int main(void)

{

    init_hardware() ;

    for(;;)

    {

        if (adc_done_flag) {

            adc_done_flag = 0 ;

            CyDelayUs(100) ; /* 100us */

            ADC_Done_Write(0) ;

        }

    }

}

=====================

So it seemed that I get only 1 ADC conversion with this configuration.

NOTE: I also tested with CyDelayUs(1) ; /* 1us */

still I got only 1 pulse during the clock cycle.

moto

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

It was my bad, I missed that "1kHz" was input.

So I changed the 1kHz clock with an external Digital Input.

And I connected the input to the Oscilloscope's 1kHz calibration signal.

NOTE: For me there was no change in the result.

So I imagine that may be you had some bouncing in the clk in your original post.

Oscilloscope

IMG_4296.JPG

Schematic

010-schematic.JPG

Pins

011-pins.JPG

ADC configuration (not changed but just in case)

012-adc_config.JPG

main.c

================

#include "project.h"

volatile int adc_done_flag = 0 ;

CY_ISR(adc_done_isr)

{

    adc_done_flag = 1 ;

    ADC_Done_Write(1) ;

}

void init_hardware()

{

    CyGlobalIntEnable; /* Enable global interrupts. */

    isr_ADC_ClearPending() ;

    isr_ADC_StartEx(adc_done_isr) ;

   

    ADC_SAR_1_Start() ;

}

int main(void)

{

    init_hardware() ;

    for(;;)

    {

        if (adc_done_flag) {

            adc_done_flag = 0 ;

            CyDelayUs(1) ; /* 1us */

            ADC_Done_Write(0) ;

        }

    }

}

================

moto

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Hi Motoo,

Thanks for your help, it give me a better picture of this component.

Regards.