PSoC 63 SPI slow speed

[JaWa_4152831]

operating system: WINDOWS 10

IDE: PSoC creator 4.2

MCU: CYBLE-416045-02

SPI component version 2

PDL: 3.1.0

I am using SPI in Master mode

CPHA 0

CPOL 0

Data Rate 25000 kbps

Oversample 4

the actual data rate is 6250 ksps

if I remove MISO I can set oversample to 2 but I need MISO

I need at least a sample rate of 1200 ksps how can I increase the speed of the SPI?

is 6250 ksps the maximum sample rate?

is there a way I can override the oversample to be 2 while keeping MISO?

how can I increase my data rate?

if 6250 ksps is the top speed then why does the datasheet boast a 25000 ksps spi bus?

[BragadeeshV]

Hi JaWa_4152831​,

When MISO is enabled, the oversampling factor can be between 4 to 16. The desired output frequency depends on the input clock source to the SCB block and the oversampling factor. ie desired SPI freq = SCB Clk freq/ Oversampling.

To achieve 25 Mbps with minimum allowable oversampling of 4, set the input clk_peri to 100 MHz (25 x 4) as shown using clock configurator:

Regards,

Bragadeesh

[JaWa_4152831 · Accepted solution]

Thanks that helpedmI had to do that and also I edited the HF clock that feeds CLK_Peri it had HF clock was set to 50 it is now 100 and oversample 4 sets spi clock to 25Mhz! yay. FYI local clocks (perifrials) cannot be edited they are grayed out. only the upper clocks (currently in yellow) can be edited.