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What is the Soft Error Rate (SER) for the S70GL02GT? Also, is this device susceptible to Single Event Latchup (SEL)?
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Parallel NOR
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Hi Tommy,
Please find SER and SEL information below -
Accelerated Alpha Particles
Process Technology | Product Family | SER (FIT/Mb) | SEL (FIT/Dev) | |
SBU | MCU | |||
45nm MirrorBit NOR | Flash w/o ECC | < 0.7 | < 0.07 | N/A |
Flash w/ ECC | < 0.007 | < 7e-4 | N/A |
Accelerated Neutrons/Protons
Process Technology | Product Family | SER (FIT/Mb) | SEL (FIT/Dev) | |
SBU | MCU | |||
45nm MirrorBit NOR | Flash w/o ECC | < 0.7 | < 0.07 | < 10 |
Flash w/ ECC | < 0.007 | < 7e-4 | < 10 |
Regards,
Apurva
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Hi Tommy,
Please find SER and SEL information below -
Accelerated Alpha Particles
Process Technology | Product Family | SER (FIT/Mb) | SEL (FIT/Dev) | |
SBU | MCU | |||
45nm MirrorBit NOR | Flash w/o ECC | < 0.7 | < 0.07 | N/A |
Flash w/ ECC | < 0.007 | < 7e-4 | N/A |
Accelerated Neutrons/Protons
Process Technology | Product Family | SER (FIT/Mb) | SEL (FIT/Dev) | |
SBU | MCU | |||
45nm MirrorBit NOR | Flash w/o ECC | < 0.7 | < 0.07 | < 10 |
Flash w/ ECC | < 0.007 | < 7e-4 | < 10 |
Regards,
Apurva
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Thank you for the information Apurva.
Would you be able to provide more details on the accelerated testing? Is there a test report available? In particular, for the SEL rate, I am looking for the number of devices tested, the total fluence applied during testing, and the number of latch up events observed during the accelerated testing.
Thank you.