Method to using a lower speed clock on the FX3 Explorer sync slave FIFO interface?

[PaKa_4615756]

I  ported the AN65974\FPGA Source files\fx3_slaveFIFO2b_altera\fpga_streamIN design to an Altera EP3C5 board that my Superspeed Explorer card mounts to.

Using the sync_slave_fifo_2bit.cyfx example GPIF state machine with the cyfxslfifosync example firmware and my FPGA-generated PCLK of 80MHz, the set up works

fine with USBControlCenter.

But I have some DAQ in my eventual application that wants to lollygag along at 40MHz. Reprogramming the 3C5 for 40MHz PCLK, I am unable to find a combination of clockConfig.mmioClkDiv, pibClock.clkdiv, gpifclkdiv, clockConfig.dmaClkDiv, and clockConfig.cpuClkDiv that works with the example firmware&GPIF setup. In some instances the logic analyzer captures a "runt" frame on the FIFO interface on download of the firmware followed by ...nothing. In other cases, the interface is simply dead

(Always using USBControlCenter data transfers to tickle the FX3).

What method is there to successfully using a lower speed clock on the FX3 Explorer sync slave FIFO interface?

[Hemanth]

Hi,

- Can you please let me know what changes are done to pibClock and clkCfg for 40MHz when compared to 80MHz? - Usually no change is required for these for sync slave mode.

- Have you seen symptom 1 of Appendix A in https://www.cypress.com/file/136056/download​?

- Can you provide more details on what the issues mentioned - "logic analyzer captures a "runt" frame on the FIFO interface on download of the firmware followed by ...nothing" and "the interface is simply dead"?

Regards,

Hemanth

[PaKa_4615756]

Yes, the call to CyU3PUsbLPMDisable() is present exactly as in "Symptom 1" in the AN65974 appendix.

I have an Agilent logic analyzer watching PCLK, slwr, flaga, flagb, slcs, and dq0, triggering on H>L transition of slwr. A normal 32b frame at 80MHz on the FPGA>GPIF interface is 256 PCLKs requiring 3200ns.

For a dead interface, after loading the FX3 with the example code, "TRANSFER DATA IN" responds with a timeout and the analyzer does not trigger.

For a runt frame, the analyzer triggers when the firmware is downloaded but not for any subsequent "TRANSFER DATA IN" requests. The runt frame has all signals sequencing as expected but for only 9 to 16 PCLKs. The number of PCLKs is not consistent.

I have tried the following with 40MHz PCLK:

All dividers set to default except DMAdiv=2 > runt; DMAdiv=4 > dead; DmaDIV=3 > dead; DMAdiv=8 > dead

All dividers set to default except PIBdiv=4 > runt; PIBdiv=8 > runt

and some other combinations that I failed to include in my notes.

The FX3 is a stock SuperSpeed Explorer. My base board is a Cyclone III EP3C5 with a 40MHz oscillator driving one of its PLLs and thence to PCLK. FPGA code is downloaded using a USB-Blaster.

[Hemanth · Accepted solution]

Hi,

Referring to the below comment:

"For a dead interface, after loading the FX3 with the example code, "TRANSFER DATA IN" responds with a timeout and the analyzer does not trigger"

>> Since the analyzer did not trigger, I suspect the issue to be on the FPGA side.

"The runt frame has all signals sequencing as expected but for only 9 to 16 PCLKs. The number of PCLKs is not consistent."

>> Are the PCLKs from the FPGA not consistent?

Both of the above seems to be a problem on the FPGA side. From your previous comment, I think the data width you are using is 32bit and PCLK is provided by the FPGA. Can you please share the analyzer trace that you have recorded?

Regarding the DMAdiv, as of now you can maintain the same as it was for 80MHz case.

To support 40MHz, I think the changes are only done on the FPGA side. Please confirm.

Regards,

Hemanth

[PaKa_4615756]

Taking your clue, I removed the delay-locked-loop between the PLL and the PCLK pin. 32b transfers now work reliably at 40MHz.

Thanks!