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I have a feature request! The SCB SPI block only supports data sizes from 4 to 16 bits. Could Cypress grow this to 32 bits?
How to support 32-bit transfers has been asked before a few times:
SPI Master 3~16 bit width limit!
so this seems common enough to warrant a feature request instead of a one-off fix. So far the answer has been to "send two transfers, but also manually control slave select so that the slave doesn't see the end of the transfer", or maybe write your own in UDB. It would be nice to have it work out of the box, and without requiring CPU control of the SS line (to indicate end of data block) where it may compete with other interrupts.
Solved! Go to Solution.
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Hi NiLe_4630071,
If you are using PSoC Creator 4.x, then you would find the option "Deassert SS Between Data Elements" option. Keep this option unchecked for continuous transfer.
If you are using MTB 2.x, you will find the same option in the device configurator:
Regards,
Bragadeesh
Bragadeesh
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Hi NiLe_4630071,
You can still send 32 bit data using the continuous transfer option that will keep the CS line low as long as the transaction is complete. You can send two 16 bits data using an array and this doesn't require manual control of SS line.
Moving to a 32 bit data bit per frame would require creating a new block at design phase. We will file an internal enhancement request for the same. Thank you for your interest with Cypress products
Regards,
Bragadeesh
Bragadeesh
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Thank you for filing the internal enhancement request!
Could you point me to documentation that describes the "continuous transfer" mode? I looked at the SCB SPI master data sheet and didn't find the continuous transfer option?
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Hi NiLe_4630071,
If you are using PSoC Creator 4.x, then you would find the option "Deassert SS Between Data Elements" option. Keep this option unchecked for continuous transfer.
If you are using MTB 2.x, you will find the same option in the device configurator:
Regards,
Bragadeesh
Bragadeesh