Current spike on FB pin of CYPD3175

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BDu_4573986
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Hello,

I am using CYPD3175 (24-pin QFN) in a USB-PD direct feedback DC/DC application. I am experiencing issues with a current spike dished out on the FB pin on positive VBUS transitions to, and exceeding, 20V.

To step up the DC/DC output voltage from the initial 5V Vsafe setting, the USB-PD controller needs to pull current from the FB node (let's assign a negative connotation to current leaving the FB node), which it does. However, the control current steps are associated with transitory initial positive disturbances (current flowing into the FB node) of varying magnitude, likely due to internal (to CYPD3175) switching of current source paths to ground or whatever D/A circuitry is being used to generate it.

I have been able to isolate the offending disturbance to a very finite step in the (VOUT/VBUS) voltage transition: 20.34V to 20.36V, in the firmware and circuit I use. The expected 100nA increase in the negative FB current is preceded, in this case, by a >10uA positive current spike, high and long enough to trigger OVP in the DC/DC controller.

Filtering the FB node using a capacitor to ground is not a great option, since it creates a pole, at relatively low frequency, in the feedback loop.

It appears to me this is an issue related to how the FB control sink current is generated, a hardware issue within the CYPD3175. Is there anything that can be done in software to mitigate this problem?

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ShifangZ_26
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Hi ,

Could you please kindly use UART transmit out the value of IDAC write in the API?

void pd_hal_set_fb_dac(int16_t dac_value)

{

    uint32_t tmp;

    tmp = PDSS->ea_ctrl & ~(

            PDSS_EA_CTRL_ISRC_DAC_CTRL_MASK |

            PDSS_EA_CTRL_ISNK_DAC_CTRL_MASK |

            PDSS_EA_CTRL_ISRC_EN |

            PDSS_EA_CTRL_ISNK_EN);

    if(dac_value >= 0)

    {

        tmp |= ((dac_value << PDSS_EA_CTRL_ISNK_DAC_CTRL_POS) &

                PDSS_EA_CTRL_ISNK_DAC_CTRL_MASK);

        /* Enable only for non-zero value. */

        if(dac_value != 0)

        {

            tmp |= PDSS_EA_CTRL_ISNK_EN;

        }

#if (VBUS_CTRL_TYPE_P1 == VBUS_CTRL_DIR_FB)

        if (ccg_get_si_revision() != 0)

        {

            PDSS_TRIMS->trim_ea1_0 = EA_IREF_GAIN_NDAC;

        }

#endif /* (VBUS_CTRL_TYPE_P1 == VBUS_CTRL_DIR_FB) */

    }

    else

    {

        tmp |= ((((dac_value * -1) << PDSS_EA_CTRL_ISRC_DAC_CTRL_POS) &

                PDSS_EA_CTRL_ISRC_DAC_CTRL_MASK) | PDSS_EA_CTRL_ISRC_EN);

#if (VBUS_CTRL_TYPE_P1 == VBUS_CTRL_DIR_FB)

        if (ccg_get_si_revision() != 0)

        {

            PDSS_TRIMS->trim_ea1_0 = EA_IREF_GAIN_PDAC;

        }

#endif /* (VBUS_CTRL_TYPE_P1 == VBUS_CTRL_DIR_FB) */

    }

    PDSS->ea_ctrl = tmp;

}

As you know, the DAC is value is for SINK or SOURCE, you could find out whether the root cause is IDAC value is too large or not.

Best Regards,

Lisa

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Hi Lisa,

Forgot to mention my experience is with power conversion, power electronics, all on the hardware side. I am at a total loss understanding your feedback.

I have attached the firmware file - if it does not help you, let me know what should I do, step-by-step, to provide you with whatever information you need. I did not create this firmware file, but I have another one that I created, using advice from this forum, which has the same issue (did not track down to the exact voltage step, but any transition to 20V or above creates the same spike on FB).

Thank you.

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Lisa,

Just to re-iterate: the magnitude of current steps out of the internal DAC, which control the change in VOUT/VBUS are fine. The firmware I attached to this previous reply steps in the minimum increment of ~100nA every 200us (VOUT change of 20mV every 200us), and I have also seen the circuit work fine with what appeared to be 2.5uA steps (0.5V VOUT step change) every 1ms, or so.

The issue is related to the apparent 'noise' spikes if you will, which occur when certain steps are initiated. Most of them are not large enough to trigger the DC/DC protection. However, there is one which stands out, being much larger than all others, which creates a disturbance of ~600mV amplitude at the FB node and triggers the protection mechanism.

These 'noise' spikes are of opposite magnitude to the control current. For stepping VOUT high, the control (IDAC) current is negative, flowing to the ground. These errant spikes, including the one that shuts down the DC/DC, are positive, flowing into FB.

Hope this clarification helps.

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Hi ,

With your clarifying, Is it recommending to add a constraint inside of CCG3PA firmware for FB's IDAC? If my understanding is correct, please kindly notice that the voltage adjust is not jump, we have a 300mV constraint for target and the FB rising slew is controlling in the file psource.c.

Best Regards,

Lisa

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