5 Replies Latest reply on Apr 7, 2020 12:55 AM by JayakrishnaT_76

    GPIF thread arbitration

    WGT_4383351

      When multiple state transition path's condition are met, how does GPIF engine choose the next state?

       

      For example, in the Master/Slave example in AN87216, in the master's state machine, if both master to slave data and slave to master data in valid, will RD_WR_IDLE go to WR_FLAG or DR_ADDR?

        • 1. Re: GPIF thread arbitration
          JayakrishnaT_76

          Hello,

           

          The transition from one state to another depends on the transition equation. Your understanding is correct that when the master state machine is in the state RD_WR_IDLE, it can either undergo a transition to WR_FLAG or DR_ADDR. This depends on the transition equation. If both DMA_RDY_TH1 and FLAG_B are asserted, then the state machine undergoes a transition to WR_FLAG and if FLAG_A is asserted, then it undergoes a transition to DR_ADDR state.

           

          Best Regards,

          Jayakrishna

          • 2. Re: GPIF thread arbitration
            WGT_4383351

            What if DMA_RDY_TH1 and FLAG_B and FLAG_A are all asserted? That's the focus of the question.

            • 3. Re: GPIF thread arbitration
              JayakrishnaT_76

              Hello,

               

              It seems like this condition wont happen. Please find my comments below:

              1. In general DMA Ready flag indicates if a buffer has got some data that can be read from it or the buffer has some space so that data can be written to it.

              2. Consider the Master's GPIF project, as you may be knowing GPIO 21 is connected to FLAG A, GPIO 23 is connected to FLAG B and GPIO 25 is connected to FLAG C. FLAG A, FLAG B and FLAG C are GPIO 21, GPIO 23 and GPIO 25 of slave GPIF project. Now, GPIO 21 of slave is configured as a ready flag for thread 1, GPIO 23 is configured as a ready flag for thread 0 and GPIO 25 is configured as a partial flag for thread 1. For slave, socket 1 is a consumer socket that is this socket receives data from U Port from slave's control center. But, socket 0 is producer, that is this socket receives data from master's P Port and then sends it to U Port of slave's control center. So we can characterize both these as two:

              a. Write to slave FIFO: Here the master writes data into slave's socket 0 which is finally transferred to U port of slave.

              b. Slave FIFO Read: Here, the master reads data from slave's socket 1 which is finally transferred to U port of master.

               

              When any non-empty buffer is associated with socket 1 of slave, FLAG A will be asserted. A non empty buffer will be associated with socket 1 of slave only when we transfer data from U Port to P Port of slave using control center. 

              Similarly, when there is space in a buffer associated with socket 0 of slave, FLAG B will be asserted.

               

              3. Now consider the state machine for Master GPIF project. When the state is RD_WR_IDLE, the state machine checks for the transition equation to jump to the next state. From what was mentioned before in this response, if you try to transfer data from slave to master or slave FIFO read, FLAG A will be asserted and this will switch the state machine to DR_ADDR state.

              If you try to send data from master to slave, then DMA_RDY_TH1 will be asserted and if the buffers associated with socket 0 is empty, then FLAG B will also be asserted. This means that the state machine will jump to WR_FLAG state.

               

              So, the jump basically depends on who initiated the transfer and whether the consumer has enough space in the buffer to receive the data. Chances are rare that both transition equations are triggered together and we havent seen such an issue.

               

              Best Regards,

              Jayakrishna

              • 4. Re: GPIF thread arbitration
                WGT_4383351

                What will happen if in some designe of state machine where two branch's condition are both met?

                • 5. Re: GPIF thread arbitration
                  JayakrishnaT_76

                  Hello,

                   

                  Please refer to Page 138 section 7.4.3 of FX3 TRM. This can be found in the following location:

                  C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\firmware

                   

                  Accordingly, if two transition equations are met, then the state machine will transition to the left state always. The left and right state for a given state can be identified by checking the structure CyFxGpifWavedata in .h file generated by GPIF designer. The following snippet shows CyFxGpifWavedata for Master Project.

                   

                   

                  In each row, first 12 bytes are Left Edge Waveform Memory Register and the remaining 12 bytes are Right edge Waveform Memory Register. These register values can be used to understand the left and right states. More information on this register can be found from page 362 of FX3 TRM.

                   

                  Please note that if 2 transition equations are met simultaneously, the state machine will always transition to left state. So, please make sure that such a condition does not occur in your design to avoid unwanted results.

                   

                  Best Regards,

                  Jayakrishna

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