I will clarify the process of enabling/disabling four byte address mode and quad mode for the Cypress Flash Devices mentioned.
There are three ways in which extended addressing can be enabled for these parts -
The Bank Address Register configuration is as follows -
- By default, the EXTADD bit of Bank Address Register (BAR) is set to zero. In this case, all legacy SPI commands expect only 3 bytes of address and the higher order address bits are supplied from the BAR (The default values for these higher order address bits A25 and A24 are also zero as shown in the table above). These A25 and A24 bits can be programmed to some other value (one) using the BRWR (17h) command.
- The second configuration is when the EXTADD bit is programmed to one. In this configuration, the A25 and A24 bits are not supplied from the BAR, and all legacy SPI commands expect 4 bytes of address after the command byte.
- The third method of addressing is by using the new commands.
Let us take READ command as an example to understand this.
- 03h command expects 3 bytes of address when EXTADD bit of BAR is set to zero. The higher order address bits are being supplied by the BAR.
- 03h command expects 4 bytes of address when EXTADD bit of BAR is set to one. Complete 4 bytes of address need to be provided after the command byte.
- 13h command can be used directly followed by 4 bytes of address without making any changes to the BAR.
There are two ways in which extended addressing mode can be enabled for this part -
We can understand this using explanation for READ command.
- 03h command expects 3 bytes of address when the CR2V of Configuration Register 2 is set to zero.
- 03h command expects 4 bytes of address when the CR2V of Configuration Register 2 is set to one.
- 13h command can be used followed by 4 bytes of address without making any changes to the Configuration Register.
All the above mentioned devices (S25FL512S/S25FL256S/S25FS256S) follow the same method for enabling/disabling the Quad mode. The QUAD bit (Non Volatile bit) in the Configuration Register 1 needs to be set or reset to enable or disable Quad mode respectively. Please note that the Single SPI commands still continue to work even when Quad mode enabled.
Hope this answers your query. If not, please feel free to reach out.
This explains the usage of S25FLS 4byte. Do you understand that the commands to enter and exit 4 byte addr mode of 256 / 512Mb flash of MICRON(MT25QL512ABB8E12-0SIT) are the same as Cypress(S25FL512S)?
Cypress S25FL512S does not have the following commands to enter 4-BYTE ADDRESS MODE Operations of Micron.
4-BYTE ADDRESS MODE Operations
･ENTER 4-BYTE ADDRESS MODE: B7h
･EXIT 4-BYTE ADDRESS MODE: E9h
Cypress S25FL51S accepts 32bit addresses by inputting the following 4Byte Address command.
No prior register setting is required.
Also, there is no need for 4-BYTE ENTER / EXIT commands like Micron.
Thanks and regards,