Does the NXP iMXRT1050 family support HyperRAM, HYper Flash, combination devices?

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MaRe_4628281
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Hello,

The answer to a prior discussion said that the iMX RT family supports both hyperram and hyperflash:

  1. i.Mx RT Platform Memory Recommendations

A few key questions remain.

1. Does imxrt1050 support combination devices such as S71KL256SC0BHB000?

1.1 Will a 166Mhz, 1.8V combination device become available in the future?

2. Does imrt1050 support both a hyperflash and a hyperram device on the same 8 bit FlexSPI bus?

2.1 Assuming so, will the combination degrade the performance of either?

3. Role of the RWDS signal, A_DQS in iMRT1050 documentation.

Hyperflash documentation describes RWDS as a read data strobe driven by the flash device.

Hyperram documentation describes RWDS as both a read strobe driven by the RAM and as a cycle timing signal and data mask driven by the processor.

But iMRT1050 documentation, reference manual chapter 27.4, table 27-4, describes the signal mainly as an input to the processor.  Its function as an output does not seem compatible with section 3.3 of the HypeBus Specification, which describes the processor driving the signal as a data mask during write transactions.

Does the iMXRT1050 properly drive RWDS to operate HyperRAM with maximum throughput?

Thank you,

M.Reich

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1 Solution

Hello,

Please find answers for your queries below.

  1. Our Hyper devices in 65nm MirrorBit in 1.8V are all available and in Mass-Production, i.e. HyperRAM S27KS-S, HyperFlash S26KS-S and HyperMCP S71KS-S. All these devices runs up to 166Mhz DDR at 1.8V.

  2. There is no performance or reliability difference between two separate devices (HyperRAM and HyperFlash) and HyperMCP.

    HyperMCP offer the possibility to use a single package which reduce board space.

  3. The same RWDS signal needs to be connected to both the HyperFlash and the HyperRAM. Only one single RWDS is needed and shared between HyperRAM and HyperFlash.

  4. Please see the following application note from NXP "How to Enable HyperRAM with i.MX RT" for more details about interfacing HyperBus memories with iMXRT devices. It is available at: https://www.nxp.com/docs/en/nxp/application-notes/AN12239.pdf.

Thanks and Regards,

Sudheesh

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SudheeshK
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250 sign-ins First question asked 750 replies posted

Hello,

Our HyperFlash and HyperRAM MCP devices has 2 CS# lines, one for HyperFlash and one for HyperRAM. All other signals are shared between HyperFlash and HyperRAM. As mentioned in our website NXP iMXRT1050 supports Cypress HyperBus memories, https://www.cypress.com/hyperbus-chipset-support​ .

We already have a 1.8V, 166MHz HyperFlash and HyperRAM MCP device. Please check S71KS512S, https://www.cypress.com/file/322936/download

As your remaining queries about iMXRT1050, we request you to contact NXP for support. Please feel free to ask if you have any other related queries about our HyperBus devices.


Thanks and Regards,Sudheesh

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Hello Sudheesh,

Thank you for your answer.

Previously, I had not seen Cypress web page listing Hyperbus devices. 

The S71KS512S looks promising.  I had been investigating it.  The product data sheet lists a 1.8V, 166Mhz clock device, but it does not seem to be currently available.  When will 166Mhz clock, or faster, devices become available in this product line?

Cypress should be in a better position than NXP to discuss the requirements for a Hyperbus application that includes both RAM and flash.  The design motivating this discussion needs Hyperbus RAM, Hyperram. It would be best for the same Hyperbus to also support flash.  I’m considering both separate devices and a single device from the S71KS series. This raises two question that I’m hoping that you can answer.

  1. Are there any performance or reliability reasons to prefer a combination device over two separate device types on a single Hyperbus?
  2. You explained “Our HyperFlash and HyperRAM MCP devices has 2 CS# lines, one for HyperFlash and one for HyperRAM.”  Accordingly, the S71KS parts have two CS# lines.  Addressing two devices requires two CS# lines, so this is not surprising. The iMXRT1050 FlexSPI also has two CS# lines in 8 bit mode, called A_SS1_A and A_SS1_B.   But, the line in question is RWDS.  What capabilities and behavior (timing) does this line need to support both RAM And flash?  Does the Hyperbus controller need two RWDS lines, one for RAM, the other for flash?

Thank you,

  1. M.Reich
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Hello,

Please find answers for your queries below.

  1. Our Hyper devices in 65nm MirrorBit in 1.8V are all available and in Mass-Production, i.e. HyperRAM S27KS-S, HyperFlash S26KS-S and HyperMCP S71KS-S. All these devices runs up to 166Mhz DDR at 1.8V.

  2. There is no performance or reliability difference between two separate devices (HyperRAM and HyperFlash) and HyperMCP.

    HyperMCP offer the possibility to use a single package which reduce board space.

  3. The same RWDS signal needs to be connected to both the HyperFlash and the HyperRAM. Only one single RWDS is needed and shared between HyperRAM and HyperFlash.

  4. Please see the following application note from NXP "How to Enable HyperRAM with i.MX RT" for more details about interfacing HyperBus memories with iMXRT devices. It is available at: https://www.nxp.com/docs/en/nxp/application-notes/AN12239.pdf.

Thanks and Regards,

Sudheesh

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Hello Sudheesh,

Thank you for your answers.

A few responses follow.

  1. Please confirm availability of HyperMCP S71KS-S.  As of 20 March, Cypress, Digikey and Arrow all show that these are out of stock, with distributors showing 13 week to 15 week lead times.
    Are sampling quantities available?
  2. Thank you for confirming equivalent performance between separate devices and MCP devices.
  3. Unfortunately, NXP iMRT1050 documentation in reference manual chapter 27 does not give a complete description of DQS, which drives RWDS.   So any application information that Cypress can provide regarding performance limitation, or regarding FlexSPI configuration would be helpful, particularly for DRAM writes.
  4.   Many sources cite NXP AN12239.  It tells how to replace the HyperFlash on the iMXRT1050 evaluation board with HyperRAM. It contains a brief and incomplete introduction to HyperRAM signals and signal level protocol.  But, it does not address the question that this conversation asks; does the iMXRT1050 properly support both HyperRAM And HyperFlash on the same 8 bit FlesSPI bus.  Any information that Cypress could contribute to this question would be most helpful

Thank you,

M.Reich

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Hello,

NXP has successfully tested our HyperFlash, HyperRAM and HyperMCP devices on iMX RT1050 MCU. We recommend you to contact NXP for further assistance.

I will get back to you with details about the availability of HyperMCP S71KS-S as soon as possible.

Thanks and Regards,

Sudheesh

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Hello Sudheesh,

Thank you for your answers.

Can Cypress provide advice on signal integrity design when using both a HyperRam and Hyperflash device on a single bus. Does Cypress advise using the combination device to avoid difficult signal integrity issues, or is the main advantage of the combination device simply board area?

Thank you,

M.Reich

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Hello,

As we informed you earlier the main advantage with HyperMCP is the reduced board space.

"There is no performance or reliability difference between two separate devices (HyperRAM and HyperFlash) and HyperMCP. HyperMCP offer the possibility to use a single package which reduce board space."

Thanks and Regards,

Sudheesh

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Hello Sudheesh,

Yes, I understood the board space advantage. I’m asking a different question. Since these devices use clocks to 166Mhz, clocking on both edges, the bus must have good signal integrity to at least 1.3GHz. I’m asking what Cypress can advise about the relative signal integrity complexity and risk of separate vs the combined device.

m.r.

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Hello,

We recommend you to follow our layout guide for better signal integrity while using our HyperBus devices. It is available at: https://www.cypress.com/file/278156/download ​.

To check the availability of S71KS-S device, we need the complete part number that you are interested in. Please let me know the complete part number.

Thanks and Regards,

Sudheesh

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