FX3 sends data to FPGA with FlagA problem

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YaZh_4656101
Level 2
Level 2

Dear all,

Before I used EZ-USB FX2 to transfer data, FlagA was always 0.

When I press "Bulk OUT"  FlagA will change from "L" to "H" and the FPGA will receive the data.

I want to use FX3 sends data to FPGA,but FPGA never receives data.

I use logic analyzer to check the signal.Found that FlagA is always "H".

when I didn't send any data(Idle) or I press "Bulk OUT" that FlagA is always "H".

So I want to know how to make FlagA become "L".

Thanks!

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1 Solution

Hello,

From your description it seems that the FX3 is in boot loader mode.

Please refer to section 11 of this https://www.cypress.com/file/201991/download application note which mentions the state of I/O when FX3 is in boot loader mode

You need to program FX3 with the firmware attached with AN65974 application note to see the flag values

Regards,

Rashi

Regards,
Rashi

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27 Replies
Rashi_Vatsa
Moderator
Moderator
Moderator
5 likes given 500 solutions authored 1000 replies posted

Hello,

Please let me know which firmware are you using for for testing slave FIFO interface with FX3

If you are using the default firmware with the AN75974 application note, socket 3 i.e. the address lines should be 3 (binary: 11) is the consumer and Flag C  indicates the status of the DMA buffer. Flag C is high initially (Full) and it asserts low when data is read from FX3.

Please refer to AN65974 read sequence, to read data from FX3.

If you are using custom firmware, please share the project files and also the timing sequence of signals at GPIF interface

Regards,

Rashi

Regards,
Rashi
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Hello,

Thank you for your reply.

I did not use firmware to test FX3.

After FX3 is powered on, I wired to FPGA and used FPGA logic analyzer to see the output signal of FX3.

I found that the FlagA signal has always been "H". I just watched the FlagC signal and it will continue to have irregular "H" "L" conversions.

I want to know if the FX3 hardware settings are wrong or other problems.

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Hello,

From your description it seems that the FX3 is in boot loader mode.

Please refer to section 11 of this https://www.cypress.com/file/201991/download application note which mentions the state of I/O when FX3 is in boot loader mode

You need to program FX3 with the firmware attached with AN65974 application note to see the flag values

Regards,

Rashi

Regards,
Rashi

Hello,

I read your reference file and I also think my FX3 in boot loader mode.

I have tried some operations.

I used the "USB Suite" example(USBBulkLoopAuto) and program it to FX3 with "USB Control Center"(Program→FX3→RAM).

I tested that "Bulk out endpoint (0x01)" can send data and "Bulk in endpoint (0x81)" can receive data, but the flag signal and other control signals remain unchanged, and the data is not sent to the FPGA.

This operation can program the firmware into FX3, but still can't enable FX3.

I want to know how to enable FX3 or which firmware should be program into FX3.

Hope you can tell me the steps in more detail.

Thanks!

USB_Control_Center.JPG

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Hello,

Bulkloopauto FX3 example firmware is to implement a data loopback application over a pair of USB bulk endpoints.

The device enumerates as a vendor specific USB device with a pair of bulk endpoints (1-OUT and 1-IN).  The application loops back any data that it receives on the bulk OUT endpoint on the bulk IN endpoint.

For FPGA to USB or USB to FPGA transfer. You need to use slavefifosync firmware attached with the application note AN65974 (AN^5974.zip)

https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

Please refer to the GPIF interface and probe the GPIO's which are used as flags

slavefifo_an.PNG

So try programming FX3 with this firmware (Path:..\001-65974_AN65974 \AN65974\FX3 Firmware\SlaveFifoSync\Release\SlaveFifoSync.img) and probe appropriate flags

Regards,

Rashi

Regards,
Rashi

Hi, I bought two superspeed kits, one works fine, but another doesn't, which has the same problem for FlagA. When I changed FlagA from GPIO_21 to GPIO_22, It works fine. It may have  hardware problem.

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Hello,

Thank you for your file. FX3 can change flag signal.

I use the firmware and Verilog Code from you provided, and FPGA can receive data.

But flag and other signal is weird,and there is a problem receiving the data of USB_DATA.

I sent usb_data.

12333.JPG

received data by FPGA.

FPGA.jpg

The green circle indicates that the data received is correct.

The red circle indicates that the data received is wrong.

E.g:

The data received should be 0x03020100, but received is 0x00020100.

The data received should be 0x07060504, but received is 0x07060500.

The next data is correct(0x0B0A0908 and 0x0F0E0D0C) .

After that, the "sloe" and "slrd" signals became 1 and the data was wrong(Clock from 6 to 46).

Clock from 47 to 49 is correct(0x13121110 and 0x17161514).

Clock from 49 to 69 is wrong.

Clock from 69 to 70:data received should be 0x1B1A1918, but received is 0x1B1A1818.(flag_c is 1)

Clock from 70 to 142 is wrong.

data is missing 0x1F1E1D1C.

next data received should be 0x23222120, but received is 0x20222100.

next data received should be 0x27262524, but received is 0x27262520.

Clock from 144 to 146 is correct( 0x2B2A2928 and 0x2F2E2D2C.)

next data received should be 0x33323130, but received is 0x3F363D34.

next data received should be 0x37363534, but received is 0x37363530.

next data received should be 0x3B3A3938, but received is 0x3B3E3938.

next data received should be 0x3F3E3D3C, but received is 3F3A3D3C.

.......etc.

Every time I send the same data(00~5F), and FPGA receive the same wrong character.

I do n’t know what went wrong, the error rate is very high, but I found the Flag signal was unstable.

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Hello,

Please let me know how are the switch on spartan configured to configure the FPGA in one of the four FPGA transfer modes mentioned in table 6 of section 11.5

Regards,

Rashi

Regards,
Rashi
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Hello,

The FPGA board model I use is DE10-standard.

It seems that no switch in the table 6 of section 11.5 can be set.

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Hello,

If you are not using Spartan 6 or Altera FPGA, you need to modify the verilog code to switch between the FPGA transfer modes.

As per the state machine running on FPGA, if the modes are not switched, the FPGA will be in idle mode

modes.PNG

In default verilog/VHDL code, the status of the switch (on Spartan6 or Altera board) will decide the FPGA transfer mode. so please modify the FPGA code and then check the Data transfer as per the mode

Please refer to this table and transfer the data accordingly. For USB> GPIf (FPGA) transfer Stream Bulk OUT mode needs to be chosen. for this the Full packets needs to be sent through USB. 512 bytes for USB 2.0 and 1024 bytes for USB 3.0. also in the firmware the macro STREAM_IN_OUT needs to be enabled

table6.PNG

Regards,

Rashi

Regards,
Rashi
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Hello,

If I want to use Stream OUT mode, do I need to use other signals to trigger?

2020-03-28_160729.jpg

Or I need to modify the verilog code for the switch?

I use the "Stream OUT" example code for transmission testing, but the flag is very unstable, resulting in unstable data transmission.

So I want to have some ideas on how to modify the verilog code.

Thanks.

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Hello,

In the verilog code (Path: ..\001-65974_AN65974 (3)\AN65974\FPGA Source files\fx3_slaveFIFO2b_xilinx\rtl_verilog\slaveFIFO2b)

- this is the top module slaveFIFO2b_fpga_top.v which has the input mode_p, based on the switched on the SPARTAN 6 board

mode.PNG

According to the status of these switches (on the SPARTAN 6 board) or the value of mode_p the FPGA transfer modes are switched and appropriate module is instantiated.

mode_1.PNG

So, the verilog coed need to be modified such that

next_fpga_master_mode = fpga_master_mode_stream_out;

and stream_out module instantiation is done

selction.PNG

STREAM_OUT transfer mode allows full packets to be transferred fro USB to FPGA i.e. for USB 2.0 packet size will be 512 bytes and for USB 3.0 packet size will be 1024 bytes. So please try sending full packet data after modifications to verilog code.

If I want to use Stream OUT mode, do I need to use other signals to trigger?

>> Only instantiation of slaveFIFO2b_streamOUT module need to be confirmed. No other triggers are required.

- Please program the FX3 first and then the FPGA

- Also check the FLAG status before transferring data (after programming FX3 and then FPGA)  and let me know the results

Regards,

Rashi

Regards,
Rashi

Hello,

I have some questions after reading the code.

The board I used is Altera DE10-standard and my input clock is 50MHz.

2020-03-30_203020.jpg

But the code's PLL module input clock is 27Mhz to 100MHz, so do I need to regenerate a new PLL module with 50MHz to 100MHz?

2020-03-30_203838.jpg

What's the purpose of this module? I can't find the code of this module(ODDR2.v)  in the folder.

Can I use the inversion of the PLL output clock(~clk_100) as clk_out?

2020-03-30_204710.jpg

I want to use Stream OUT mode,so should I changed "mode <= mode_p" to "mode <= STREAM_OUT"?

Or is there other way to make the input signal "mode_p" become STREAM_OUT?

2020-03-30_205712.jpg\

2020-03-30_205956.jpg

Thanks!

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Hello,

But the code's PLL module input clock is 27Mhz to 100MHz, so do I need to regenerate a new PLL module with 50MHz to 100MHz?

>> The 27MHz to 100MHz PLL is used as clk out is kept as 100 MHz to use the maximum data throughput of GPIF II interface. GPIF II can support frequency of 100 MHz. You can use different PLL but it would be to keep the clkout near to 100MHz to get higher data throughput.

What's the purpose of this module? I can't find the code of this module(ODDR2.v)  in the folder.

Can I use the inversion of the PLL output clock(~clk_100) as clk_out?

>> Please refer to this document https://www.xilinx.com/support/documentation/user_guides/ug381.pdf for ODDR2

Solved: Question about ODDR2 - Community Forums

I want to use Stream OUT mode,so should I changed "mode <= mode_p" to "mode <= STREAM_OUT"?

Or is there other way to make the input signal "mode_p" become STREAM_OUT?

>> yes, you can assign  3'd4/ STREAM_OUT to mode

Regards,

Rashi

Regards,
Rashi
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The FPGA I used is Altera.It is not xilinx, do I still need to use ODDR2?

I read the information to understand that the purpose of ODDR2 is to allow the clock output of the PLL to be output to the GPIO through ODDR2.

I searched some information, ODDR2 is used for xilinx.

If Altera's FPGA can directly output the PLL clock, do I still need to use ODDR2?

Thanks!

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Hello,

If Altera's FPGA can directly output the PLL clock, do I still need to use ODDR2

>> If FPGA is  able to get direct clock from PLL directly, then ODDR2 is not needed. To confirm the clock is proper probe the clock out pin and check the frequency of the clock

Regards,

Rashi

Regards,
Rashi
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Hello,

After using slaveFIFO2b_fpga_top code, I can fully receive the data of BULK-OUT(00~FF).

(clk is input clock and it is 50MHz,and Observed clock is 100MHz)

2020-04-02_155624.jpg

2020-04-02_160707.jpg

But the failure rate is very high, often the FPGA does not receive data after BULK-OUT.

If the FPGA does not receive it twice, an "Error code997" will appear and the data cannot be BULK-OUT until the FX3 is re-program.

555.JPG

So I often BULK-OUT fails, and then re-program FX3 until the FPGA successfully receives the data.

I want to know why BULK-OUT often fails and how to improve.

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Hello,

Error 997 is timeout error. One of the reason of this error in your case can be that DMA buffer might not be ready/free when data is sent from USB as the DMA buffers filled (previously) may not be read by FPGA. To confirm this you can track the PROD ans CONS event in the firmware.

- Add CONS event notification

add.PNG

In DMA callback increment prod and cons variables when these event occur

add1.PNG

- Add the debug prints to get the values of prod and cons through UART

add2.PNG

Please share the debug prints after this. Also mention the DMA buffer count used with the DMA channel

Regards,

Rashi

Regards,
Rashi
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Hello,

I have added the debug code you said and build new SlaveFifoSync.img.

but I don't know how to print the values of prod and cons.

used "USB Control Center" or "EZ USB Suite"?

Thanks!

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Hello,

You can use teraterm to view debug prints.

For this you need to have UART ,of FX3, connected to PC

Regards,

Rashi

Regards,
Rashi
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Hello,

Can you tell me more detail?

How to use teraterm?

How to use UART of FX3  connect to  PC?

Is GPIO48 and 49 (UART_TX and UART_RX) connected to the UART Module and then connected to the PC?

2020-04-03_193323.jpg

Thanks!

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Hello,

Please refer to this KBA FX3: CyU3PDebugPrint Not Printing UART Debug Message - KBA229813

How to use UART of FX3  connect to  PC?

Is GPIO48 and 49 (UART_TX and UART_RX) connected to the UART Module and then connected to the PC?

>> yes you can connect only TX and RX pin to that module, but which pins will be decided according to the io matrix configuration

If the bus width is 32 bits and lpp mode is default then pins 53:56 are UART pins

conf.PNG

if bus width is 16 bits and lpp mode as default then 46:49 pins are UART pins

Please refer to fx3 datasheet

conff.PNG

Regards,

Rashi

Regards,
Rashi
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Hello,

After I refer "FX3: CyU3PDebugPrint Not Printing UART Debug Message - KBA229813", I checked my settings:

777.JPG

888.JPG

I used bus width is 32 bits,is the picture setting correct?

In addition,I want to ask questions about UART module.

I only buy two UART Modules, one is 5 volts and has "TXD RXD RTS CTS VCC (only 5V) GND", the other is 3.3 volts and only "TXD RXD VCC (3.3V or 5V) GND"

Do I need to use "RTS and CTS" for UART connection?Or only need TXD and RXD?

If necessary, are "RTS of FX3 to RTS of UART" and "CTS of FX3 to CTS of UART"?

Does GND and VCC need to be connected?

If necessary, which PIN of FX3 (V3P3, VIO or Vbus) should VCC receive? Then can GND be connected to any GND PIN of FX3?

Can FX3 support 5 volts? Or only 3.3 volts?

Thanks!

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Hello,

As you are using 32 bit bus with LPP mode as Default. GPIO [53] : [56] are the UART pins

Do I need to use "RTS and CTS" for UART connection?Or only need TXD and RXD?

>> As in uart configuration flow control is disabled you can use only UART_RX and UART_TX pins of the Uart

Does GND and VCC need to be connected?

>> You can check the datasheet of that chip and if necessary connect the GND and VCC of the FX3 to that chip

Can FX3 support 5 volts? Or only 3.3 volts?

>> UART has power domain VIO4 which can range between 1.7 - 3.6 V. For superspeed explorer kit this power domain is 3.3 V.

Regards,

Rashi

Regards,
Rashi
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Hello,

I have tried printing log with UART.

222.JPG

If the FPGA successfully receives the data, it will print "CYU3P_PIB_THRK3_RD_UNDERRUN" or "No Error : 0"

Other situations will continue to print "Prod event- 0, cons event- 0"

Maybe it didn't happen Prod or cons event.

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Hello,

This will happen when the data read by FPGA is more than the data which is in the DMA buffer (received from USB).  For stream OUT transfer, only full packets can be sent from USB. similarly, FPGA will expect 1024 bytes.

Please test this

- Program FX3

- Program FPGA

- Send 1024 bytes from control center

- check whether received on FPGA

Please take the debug prints while testing this and share the debug prints if this doesn't help

Please confirm that you are sending 1024 bytes from USB (USB 3.0 ) or 512 bytes (USB2.0).

Regards,

Rashi

Regards,
Rashi

Hello,

I sending 1024 bytes from USB (USB 3.0 ).

Now it's no problem to send data.

there is no error message "Error code: 997" and FPGA can always receive data.

Although I ’m not sure what I set,but there is no problem with the transmission.

Thank you very much for your help.

If I have other problems later, I hope you can help me.

Thanks.

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