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Green CLK 5MHz, SPI mode 0, Delay from CS Low to first hi-CLK edge is 26ns, ad the last clk edge from CS High 13ns.
Purple CS signal
Orange SOMI, the response from FRAM
An other acquisition for view MOSI output:
Green clk, orange SOMI, purple MOSI.
The micro to speak with F-RAM is TMS570LS3137.
The circuit to connect FRAM to TMS is very simple
3
I verify FRAM VDD is 3.293V.
Please can you help me?
Solved! Go to Solution.
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Hello,
Our device support SPI modes 0 and 3. In both of these modes, data change happens along with falling edge of the clock signal and data is stable during rising edge of the clock . Please see the explanation for supported SPI modes in our datasheet (https://www.cypress.com/file/41676/download , page 5).
But, in the waveform that you provided, MOSI line changes along with rising edge of the clock signal. F-RAM will not recognize command send in this mode. See the picture below.
Please configure the SPI master properly to support SPI modes 0 or 3 and try to communicate with our F-RAM.
Thanks and Regards,
Sudheesh
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Hello,
Our device support SPI modes 0 and 3. In both of these modes, data change happens along with falling edge of the clock signal and data is stable during rising edge of the clock . Please see the explanation for supported SPI modes in our datasheet (https://www.cypress.com/file/41676/download , page 5).
But, in the waveform that you provided, MOSI line changes along with rising edge of the clock signal. F-RAM will not recognize command send in this mode. See the picture below.
Please configure the SPI master properly to support SPI modes 0 or 3 and try to communicate with our F-RAM.
Thanks and Regards,
Sudheesh
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The SPI was configure PHASE 0 POLARITY 0.
I try to configure with PHASE 1 POLARITY 0 and word at 8 bit, anithing is change:
purple: SOMI
orange: SIMO
Green: CLK
PURPLE: CS
Orange: SIMO
GREEN: CLK
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Hello,
Now the waveform looks OK. The default value in status register of FM25CL64B is 0x00. So, you did not set any bit in status register, then the response from FRAM for RDSR (0x05) command will be 0x00. Did you set any of the bits in status register?
Are you able to perform write and read operations to FRAM memory? Can you try to WRITE (0x02) a known data into FRAM and READ (0x03)it back?
Thanks and Regards,
Sudheesh
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Hi,
i try to write and read. another think for use memory, signal in reset is high.
Sorry but SPI mode 0 and spi mode 3 is not a right configuration. Below table for SPI:
This memory work in SPI mode 1 or 2.
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Hello,
Are you able to communicate with FRAM after changing the SPI mode to 1 or 2 in the micro-controller?
Below 2 conditions should be met to communicate properly with our serial FRAM.
- Data should change along with falling edge of clock.
- Data sampling happens along with the rising edge of clock. Data should be stable at rising edge of the clock.
I think SPI modes 1 and 2 of the micro-controller are same as mode 0 and 3 of FRAM.
Thanks and Regards,
Sudheesh