Potential voltage confliction while stacking two CYUSB3KIT-003 - Part II

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WGT_4383351
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Sorry about the late response, now the old post can not be replied.

What about a new solution: remove 5V jumper J3 for both CYUSB3KIT-003, and wire out from both board's J3-pin2 and GND and connect to one common external 5V power source. And cut pins as described by "001-87216_AN87216_Designing_a_GPIF_II_Master_Interface.pdf". Then no problem can happen anymore, both board are supplied by the same power source at the same time. This give another benefit - easy to power cycle the two board at the same time.

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Hello,

"Since VDD is unpowered, there is no issue or damage that can be caused to the slave FX3 chip"  why?

--> VDD is the main 1.2V power supply that is used to power up the FX3 chip and since there is no voltage in the 1.2V domain, there won't be any damage to the FX3 silicon.

IO voltage violation may damage the IO pad, not related to VBUS/VDD

--> Can you please point to the exact component on the FX3 SuperSpeed Explorer Kit that you are referring to, which might get damaged?

It's not clear as to which component you are referring to by the IO pad.


Please clarify.

Regards,

Yashwant

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YashwantK_46
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Hello,

The above implementation that you have suggested can be used, but you will have to make sure that no power related pins between the two kits are shorted as mentioned in the AN87216 appnote. And you shouldn't try to connect the jumper J3 on any of the two kits when you have them working in the method specified above or else there's a chance that the host would shut off the downstream port since the current consumption would be more than what the host can supply.

Regards,

Yashwant

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WGT_4383351
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In fact the way "001-87216_AN87216_Designing_a_GPIF_II_Master_Interface.pdf" described to connect the two board may really harm the board. If the slave board is not powered on and the master board drive any control signal high (could this be possible if the slave board is powered off?) then the slave IO will be drived by the master without being powered on. In such case maximum rating is violated.

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Hello,


If the master and slave are connected as suggested in the appnote AN87216, with no connection between the power domains of the two kits, there won't be an issue of the master driving the slave IO.

Since there is no connection between the power domain pins of the master and slave, the master can't drive the slave's IO since all the power domains on the slave side are un-powered and won't respond to any of the master's signal assertions.

Also, if you can take care of the powering sequence there won't be an issue with the FX3 as slave and FPGA as master as you have mentioned above.


Regards,

Yashwant

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WGT_4383351
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For FPGA as slave, the IO on FPGA is 5V tolerent. But not true for FX3 as slave.

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"all the power domains on the slave side are un-powered" That's the problem, if the master drive any pin connected to slave high when slave is un-powered, then this violate the maximum rating, in most cast this will reverse drive the slave voltage rail to 0.x volts througth the clamping diodes in the IO pad.

"if you can take care" Power off of the PC or unplug of the board is random, you can't take care of this for every case. USB should be ready for unplug at any time.

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Hello,

Can you elaborate a bit more by what you mean "this violate the maximum rating" ?

The VIO's on FX3 are rated for a maximum voltage of 3.6V.

You can check this information in page no. 19 under Electrical Specifications column from the FX3 datsheet.

Regards,

Yashwant

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If FX3 is not powered, and you apply voltage on any IO pin, then maximum rating is violated. The driver will be clamped by diodes in IO pad to < 1 volts, but whether there will be damage is not sure.

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Hello,

I can see the same behaviour as you described on the slave side when the master is powered and the slave is unpowered where in the IO's on slave are being driven by the CTL lines on my master to some x voltages but this won't cause any damage to the chip.

Even though there is a voltage present on the V3P3 and VBUS pins, there is no voltage on the V1P2 voltage domain which is connected to the VDD pins of FX3.

Since VDD is unpowered, there is no issue or damage that can be caused to the slave FX3 chip. And also because the maximum tolerant voltage on the IO's of FX3 is 3.6 volts.


Regards,

Yashwant

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"Since VDD is unpowered, there is no issue or damage that can be caused to the slave FX3 chip"  why?

"And also because the maximum tolerant voltage on the IO's of FX3 is 3.6 volts." at the same time have to less then VDDIO+0.x volts

IO voltage violation may damage the IO pad, not related to VBUS/VDD

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Hello,

"Since VDD is unpowered, there is no issue or damage that can be caused to the slave FX3 chip"  why?

--> VDD is the main 1.2V power supply that is used to power up the FX3 chip and since there is no voltage in the 1.2V domain, there won't be any damage to the FX3 silicon.

IO voltage violation may damage the IO pad, not related to VBUS/VDD

--> Can you please point to the exact component on the FX3 SuperSpeed Explorer Kit that you are referring to, which might get damaged?

It's not clear as to which component you are referring to by the IO pad.


Please clarify.

Regards,

Yashwant

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