3 Replies Latest reply on Feb 20, 2020 1:35 AM by MoTa_728816

    I need to be able to create a down counter without interrupts


      I'm at my wit's end.  I'm trying to debug some equipment and want to simulate the problem with a PSoC5 dev board.  I want to be able to send Quadrature Encoder signals.  More specifically, I only want so many edges.   So, I put 20 into a counter, and I get 20 edges, and then it stops.  Seems simple.  I've tried using the counter as a Fixed-Function down counter, UDB counter, etc, etc.. The problem is I never  get the TC pulse.  Unfortunately, every single example I've seen either runs in Continuous mode or uses Interrupts.


      The clock, the QUADGEN_CLK is always running and never turned off, so SYNC RESET, or ASYNC RESET, shouldn't matter.


      This should be a simple -- count down and set a flag.

      I added a SR Flip-flop to hold the TC high, should it ever happen (which does not seem to be the case).



        • 1. Re: I need to be able to create a down counter without interrupts

          Hello KeDa_1385231 ,


          For a UDB counter in Down Counter  or Up Counter clock mode the edge detect logic detects the rising edge of the count input synchronous to the clock input. Depending on whether the Counter is configured as an up counter or down counter, the edge detect event on the count input increments or decrements the Counter, respectively

          The terminal count condition is met in case of down counter when counter value is equal to zero.


          Thus you need should not provide logic high to the count input of the counter


          Use the following method to provide input to the count terminal:


          I am attaching a project with one shot counter implementation as mentioned by you, please try it on the development board.

          You will notice LED blink when the terminal count is reached.




          • 2. Re: I need to be able to create a down counter without interrupts


            Attached is demo project: quadrature pulse train generator. It uses custom component ClockN, which generates train of clock pulses; each 4 clock pulses produce a single IQ pair. Project uses clock Timer to re-trigger ClockN generator at approx 125Hz rate. Quadrature frequency is controlled by Clock_1.


            Project tested using CY8CKIT-059 Prototyping Kit. All custom components are included into the project.





            • 3. Re: I need to be able to create a down counter without interrupts



              As I think the "count" input of the counter is "edge" triggered,

              I modified your schematic like below

              Note: I used CY8CKIT-059








              #include "project.h"


              void reset_quadgen(void)


                  QUADGEN_RESET_Write(0) ;

                  QUADGEN_RESET_Write(1) ;

                  QUADGEN_RESET_Write(0) ;



              int main(void)


                  CyGlobalIntEnable; /* Enable global interrupts. */


                  reset_quadgen() ;




                      CyDelay(1) ;

                      reset_quadgen() ;





              The oscilloscope output was


              I also measured GEN_CLK and it was generating about 200kHz.

              And yes, tc is asserted this time.


              So the good news is it seems to be working.

              The bad news is as I'm not familar with quad... I don't know if this is what you wanted.