I2C generated code read/write fails due to busy bus but only one master

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
JaOs_4375651
Level 1
Level 1
First like received

Hi,

The MCU is a CY8C4248AZI-L485, using an I2C component. This is a single master system with two slaves. Occasionally the two slave devices do not communicate and I tracked this down to the generated code in I2C_I2C_MASTER.c. It reads the I2C status register busy bit and returns an error if the bit is a '1'. It's seeing the I2C bus is busy (SCL is low)  but when I read this register the bit is a '0', putting a scope on the SCL line it is not low, it's pulled up as expected. The pull up resistors are pulled up to 1.8V and VDD is 3.3V. I realize 1.8V does not meet the VIH level which caused me to suspect this as the culprit. The pins have a CMOS 1.8V option which is being used but not sure it's supported for this device and/or not supported on port 4. Note that, after power cycle, the I2C bus either fails 100% of time or works 100% of the time, seems it would fail randomly. Any help would be appreciated.

0 Likes
1 Solution

Hi JaOs_4375651​,

All the devices in the bus must have the voltage levels for logic 1 and 0 as mentioned by GaneshD_41​.

PSoC 4200L provides two SIO pins - P12[0] and P12[1] that has programmable switching thresholds and programmable output pull-up voltage capability. They allow interfacing to buses and devices operating at different voltage levels.

We recommend you to use these SIO pins to interface 1.8 V for the I2C bus. Please refer to the pins component datasheet and PSoC 4200 L architecture TRM on how to use SIO pins for your application.

https://www.cypress.com/file/220321/download

https://www.cypress.com/file/218741/download

Regards,

Bragadeesh

Regards,
Bragadeesh

View solution in original post

0 Likes
4 Replies
VenkataD_41
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hi,

With CMOS the VIH and VOH levels are 0.7*VDD and 0.3*VDD respectively. Please refer page number 18 table 4 of the datasheet.

https://www.cypress.com/file/222206/download

So, please check by pulling the SCL and SDA lines to VDDD instead of 1.8 volts. If you are still facing the issue, please mention more about the 2 slaves that you are using along with the schematic.

Do you have any issue with pulling the SCL and SDA lines to 3.3 Volts?

Thanks

Ganesh

0 Likes

Thanks!

The two devices are sensors, sorry I'm not allowed to show schematics. One device has a maximum VDD of 1.98V, nominal 1.8V and will clamp the I2C lines to it's VDD. I just changed the voltage to 2.33 (.7*VDD) and still see the issue. Will try 2.43V...

0 Likes

Hi JaOs_4375651​,

All the devices in the bus must have the voltage levels for logic 1 and 0 as mentioned by GaneshD_41​.

PSoC 4200L provides two SIO pins - P12[0] and P12[1] that has programmable switching thresholds and programmable output pull-up voltage capability. They allow interfacing to buses and devices operating at different voltage levels.

We recommend you to use these SIO pins to interface 1.8 V for the I2C bus. Please refer to the pins component datasheet and PSoC 4200 L architecture TRM on how to use SIO pins for your application.

https://www.cypress.com/file/220321/download

https://www.cypress.com/file/218741/download

Regards,

Bragadeesh

Regards,
Bragadeesh
0 Likes

Okay, I suspected the issue was with the levels. The engineer who did this probably assumed it would work since PSoC doesn't show an error if the CMOS 1.8V option is used for those pins (P4.0 and P4.1). There's something in the errata about this but apparently they didn't read. My plan is to use a level shifter but may experiment with P12.0 and P12.1.

Thanks, JO