PSOC62 - Cortex M0 as main core

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JoLE_3168931
Level 3
Level 3
First like received Welcome!

Hello,

On our device prototype, based on CY8CPROTO-062-4343W, we are using the Cortex M4 core for audio processing and as this task almost fully loads it (even @150Mhz) we would like to use the Cortex M0 as the main core for all the other tasks, especially the Wi-Fi/IP management.

Before going further, I would like to know what is your opinion about this; is it feasible?

There are some examples for running user code on M0 core for MTB 1.1, however the M0 boot code is 'hardcoded' in the source code provided with MTB 2.0  (already compiled code in C array).

Thank you

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Understand you concern. cm0+ not exposed does not mean it's less reliable to run the code on it. It's just a strategy to simplify the application process through not exposing it to customer.

It's fine for you to enable cm0+ by yourself. Cypress will evaluate it to make the decision of enabling dual cores.

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ShipingW_81
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

JoLE_3168931

A similar issue - Creating a dual-core application in Modus for the 416045-02 module

Unfortunately, there is no new update over this issue and cm0+ is still not available for general user in MTB2.x.

This is very disappointing and confusing, especially when this functionality is still advertised on the PSOC 6 main page and several documents still online.

Diagram-PSoC-6-Dual-Core-MCU-Architecture_920_V4.png

Furthermore, the MTB 2.0 release notes doesn't mention this restriction, while this functionality was available on MTB 1.1 (I just ran a blinky app on the M0 core of my CY8CPROTO-062-4343W board, compiled with MTB 1.1).

Is there any technical reasons for preventing users to use the second core? (concurrent bus access issues?)

Thank you.

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JoLE_3168931
Level 3
Level 3
First like received Welcome!

Well, it took a little time but I finally managed to run and debug the entire network stack on the M0 core, with MTB 2.0.

I understand that this configuration is not supported, but my main concern is the product that we must release this year.

Moving to a faster MCU from another manufacturer is not an option, as while they are quicker they also need much more energy.

I just need to know if there’s a reason this solution is less reliable than when the code is executed on the M4.

Thank you.

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Understand you concern. cm0+ not exposed does not mean it's less reliable to run the code on it. It's just a strategy to simplify the application process through not exposing it to customer.

It's fine for you to enable cm0+ by yourself. Cypress will evaluate it to make the decision of enabling dual cores.

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