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I am trying to get this frequency in order to synchronize the CX3, on the Denebola board, with the image sensor on the e-CAM59CX3 Daughter board . I have the following configuration in mipicsi.c file:
*********************************************************************************************************
/* OV5640_YUY2_1080p : */
CyU3PMipicsiCfg_t OV5640_YUY2_1080p =
{
CY_U3P_CSI_DF_YUV422_8_2, /* CyU3PMipicsiDataFormat_t dataFormat */
2, /* uint8_t numDataLanes */
1, /* uint8_t pllPrd */
62, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_500_1000M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_8, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_8, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
0xFFFF, /* uint16_t mClkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
1920, /* uint16_t hResolution */
50 /* uint16_t fifoDelay */
};
**********************************************************************************************************
Whith this setup I can obtain the following clock frequencies, just chaging the CyU3PMipicsiPllClkDiv_t mClkRefDiv field:
CY_U3P_CSI_PLL_CLK_DIV_8 -> 147.65khz
CY_U3P_CSI_PLL_CLK_DIV_4 -> 295.32503khz
CY_U3P_CSI_PLL_CLK_DIV_2 -> 590.62530khz
So, I would like to know if it is possible to obtain this 24 Mhz performance or a near value.
Thank you so much!!!
Solved! Go to Solution.
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Hi,
The field 'mClkCtl' of the mipi config structure is incorrect. In your case it is set to 0xFFFF
MCLK out frequency = (PLL_CLK) / (MCLK_divider) / (HighByte(mClkCtl) + LowByte(mClkCtl)). In your case it would become
~ 604MHz / (2 * (256+256))
So, please correct the field accordingly.
Regards,
Hemanth
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Hi,
Have you referred to section 1.7.5 of CX3_TRM? If yes, can you let me know what is the value of PLL_CLK in your case?
Regards,
Hemanth
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Hi,
Yes, I calculated PLL_CLK with the following equation:
PLL_CLK = REFCLK * [(pllFbd + 1)/(pllPrd + 1) ] /(2^pllFRS)
Using the following values:
pllFbd = 62
pllPrd = 1
pllFRS = CY_U3P_CSI_PLL_FRS_500_1000M = 0
So, with this values I obtain PLL_CLK = 604.8Mhz. for this reason i don't know why i have a lower frequency on the mClkCtl pin, becasue into the typedef struct CyU3PMipicsiCfg_t declaration it shows that mClkOutput = PLL_Clock / mClkRefDiv.
Thanks.
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Hi,
The field 'mClkCtl' of the mipi config structure is incorrect. In your case it is set to 0xFFFF
MCLK out frequency = (PLL_CLK) / (MCLK_divider) / (HighByte(mClkCtl) + LowByte(mClkCtl)). In your case it would become
~ 604MHz / (2 * (256+256))
So, please correct the field accordingly.
Regards,
Hemanth