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Hi,
I have to transfer data from FX3 to FPGA and here i'm using AN65974 State Machine.In SM i'm using OUT_REG_CR_VALID and DMA _RDY_CT actions ,by using OUT_REG_CR_VALID i'm able to receive first 2 bytes of data in FPGA and with DMA _RDY_CT i'm getting last two bytes of data.
Find the attached snapshot below,
I'm also Refering KBA "Configuring Serial OUT Interface in GPIF of FX3 – KBA228346" based on this KBA i'm changing gpif file manually for data out to FPGA.
My question is why i'm getting this type of result and what is the function happening here?
Anyone let me know about this problem.
Regards,
Sai Kumar
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Hello,
Please check your code on the FPGA side. Also do not comment out the CyU3PPibRegisterCallback() function so that any GPIF errors will be reported. Please check if you are encountering any error on the GPIF II side.
The GPIF II state machine should not be altered. You can just define STREAM_IN_OUT in the firmware. I see you have modified the AN65974 Slave FIFO firmware, use the original firmware from the application note.
How are you sending data to the FX3? Use the control center for the same.
Best Regards,
Yatheesh
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Hello,
The DMA_RDY_CT trigger is used when the DMA is ready to send or receive data and the OUT_REG_CR_VALID is triggered when the data in the output register(EGRESS_DATA_REGISTER) becomes valid.
You can refer to the gpif2_designer_userguide in the following location: installation directory\Cypress\EZ-USB FX3 SDK\1.3\GPIFII Designer\documentation
The KBA228346 addresses transferring data over a single data line unlike the normal transfer through the 16/32 bit data bus.
Best Regards,
Yatheesh
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Hello,
What may be the reason for getting only 2 bytes Is it the problem with GPIF II Interface or FPGA side
As i mentioned before without using the actions(OUT_REG_CR_VALID and DMA _RDY_CT ) in SM i'm getting 0000 in FPGA side.
Another doubt is after programming FPGA i'm getting 2 bytes and after disconnecting and debugging (without Programming) i'm receiving next 2 bytes,with the same process i'm able to receive all bytes from FX3 two bytes at a time. Can you clarify me?
Regards,
Sai kumar
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Hello Sai kumar,
Can you please let me know why you are using OUT_REG_CR_VALID in the state machine of AN65974 which is completely based on DMA transfers.
Are you following AN65974 exactly as it is i.e. state machine and the firmware?
Please refer to the below screenshot. In the Read state, DR_DATA, is it in Socket mode?
If you are using DMA socket mode, then register based triggers are not needed.
Best Regards,
Yatheesh
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Hello,
Can you please let me know why you are using OUT_REG_CR_VALID in the state machine of AN65974 which is completely based on DMA transfers.
Without using that actions i'm not able to transfer the data to FPGA( i'm getting 0000 in FPGA side)
Are you following AN65974 exactly as it is i.e. state machine and the firmware?
Except the 2 actions remaing are same as in AN65974
Please refer to the below screenshot. In the Read state, DR_DATA, is it in Socket mode?
yes,DR_DATA, is in Socket mode only.
Regards,
Sai kumar
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Hello,
If you are using DMA socket mode, then register based triggers are not needed.
I have modified socket mode to PP Register mode in GPIF II interface,with that also i'm getting the same first 2 bytes in FPGA side.Here i'm transfering 1 KB file through control center and the flags and signals in FPGA side also triggering fine i.e., according to AN65974 read waveforms. I was Struck here,can you please let me the solution for this issue.
Regards,
Sai Kumar
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Hello,
Can you please let me know your application. Is the AN65974 implementation not working for you?
Also let me know how does your application drift from AN65974 and what changes are you making for the same?
Thanks,
Yatheesh
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Hello,
Can you please let me know your application. Is the AN65974 implementation not working for you?
My Application is transfering data from FX3 to FPGA(Zynq) and i'm using AN65974,without modifying any thing in the firmware and GPIF II Interface i'm not able to receive data in FPGA side.So,i have added OUT_REG_CR_VALID in GPIF II SM with that i'm receiving atleast 2 bytes and without that action i'm getting 0000 in FPGA side.
Please find the firmware attached below.
Regards,
Sai Kumar
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Hello,
Please check your code on the FPGA side. Also do not comment out the CyU3PPibRegisterCallback() function so that any GPIF errors will be reported. Please check if you are encountering any error on the GPIF II side.
The GPIF II state machine should not be altered. You can just define STREAM_IN_OUT in the firmware. I see you have modified the AN65974 Slave FIFO firmware, use the original firmware from the application note.
How are you sending data to the FX3? Use the control center for the same.
Best Regards,
Yatheesh