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Hello.
My customer wish to use a HyperBUS RAM.
The S6J329C has a HyperBUS ch.1, ch.2 and a HS-SPI for a graphic core.
Can it use a Hyper BUS ch.2 with a HS-SPI FLASH(G_SLK0, G_CS, G_DQ0, G_DQ1, G_DQ2, G_DQ3) for a graphic core?
The HS-SPI flash uses the 0x4000 0000 address. the HyperBUS RAM 0x4800 0000.
Can it use as above?
Thanks and Best regards.
Glenn.
Solved! Go to Solution.
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Dear author,
we have to apologize for our late response.
DDRHSSPI and HyperBus is selected exclusively by remap control.
So, you can not use HyperBUS RAM with a QSP flash simultaneously as you mentioned.
Please refer to the following KBA, as well.
Simultaneously Using HyperBus™ and QSPI Bus in Traveo™ S6J3200 Series MCU – KBA221010
thank you.
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I found the Remap register.
According to the register, The address is mapped either HyperBUS or DDR HS-SPI.
Thanks.
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Dear author,
we have to apologize for our late response.
DDRHSSPI and HyperBus is selected exclusively by remap control.
So, you can not use HyperBUS RAM with a QSP flash simultaneously as you mentioned.
Please refer to the following KBA, as well.
Simultaneously Using HyperBus™ and QSPI Bus in Traveo™ S6J3200 Series MCU – KBA221010
thank you.