The beginner who would like to operate GPIF-II interface, I recommend to read Slave FIFO interface document.
It's appplication note is called "Designing with the EZ-USB® FX3™ Slave FIFO Interface" that number is AN65974.
Thank you for your reply.
As a result, they are using it as 32-bit bus mode(GPIO:A1, GPIO:A0) of SlaveFiFO. However, since the actually required data is only the lower 8 bits, the extra 24-bit GPIF terminal is not connected.
--- Because they are using their current board ---
Q1) Since the upper unused bits (DQ  to DQ ) are not used( not connected), the value can be undefined, but is it necessary to fix the logic outside the chip? Also, is there an internal Pull-UP?
Q2) As described above, if DQ  to DQ  are not connected, are there any possible problems such as the HOST not COMMIT, etc?
If they use only lower 8bit, they can set it on GPIF-II designer. I am not clear why they set 32 bit.
FX3 has internal firmware-controlled pull-up or pull-down resistors on all digital I/O pins. An internal 50-kohms resistor pulls the pins high, while an internal 10-kohms resistor pulls the pins low to prevent them from floating.
The default state of the IOs at power-on and after reset is tristate. You can set registers or use FX3 SDK API CyU3PGpioSetIoMode to set pull-up or pull-down on an I/O pin.
Please refer to the FX3 datasheet and TRM 4.1.3 GPIO Pull-up and Pull-down. https://www.cypress.com/documentation/technical-reference-manuals/ez-usb-fx3-technical-reference-manual
>If they use only lower 8bit, they can set it on GPIF-II designer. I am not clear why they set 32 bit.
No. Read AN75779 3.5 GPIF II State Machine and modify the counter.