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I have a CYPD3120 that resets 10 ms after I turn the sink FETs on. Is there some DPM condition that needs to be met in that time period?
Below is an oscilloscope image of the issue. VBUS (yellow) is a steady 5 V when the sink FETs are enabled. The output of the FETs (blue) drops after 10 ms due to the CCG3 resetting. VSYS (Cyan) is powered from the output of the sink FETs. I've also shown an intermediate signal, USB_VBUS (magenta), which is similar to the V_SYS Oring rail on the CY4531.
To eliminate the possibility of software causing the reset, I've replaced the call to sink_fet_on with the 4 lines below. This did not change the oscilloscope plot.
CyGlobalIntDisable;
sink_fet_on(port);
CyDelay(15);
CyGlobalIntEnable;
Solved! Go to Solution.
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We discovered that the wrong capacitor had been used for the VCCD pin. It was too small a value and had too much variance with temperature. After replacing the capacitor the problem is no longer reproducible.
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Hi ,
Could you please attach CC (CC1/CC2) scope waveform also? You can remove USB_VBUS (magenta) or VSYS if you only 4 channel.
Could you please share CC log of this case?
Could you please use UART to transmit the hard-reset reason with firmware debug?
Best Regards,
Lisa
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I think my chip may have been damaged by over-temperature. I'm currently using CYPD3120-40LQXI. I see in the datasheet there is an extended industrial range for the CYPD3135-40LQXQ. Can I use this as a replacement for my upstream facing USB 3.1 Gen 1 device?
My CC analyzer is broke. I should have a new one in a couple days to get CC log.
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We discovered that the wrong capacitor had been used for the VCCD pin. It was too small a value and had too much variance with temperature. After replacing the capacitor the problem is no longer reproducible.