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GiSa_4520796
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Hello,

I want to collect the incoming data from FPGA through GPIF II .For that I am using AN65974  GPIF without any changes but I am not able to get the data that is sent from FPGA.Which GPIF II State machine is best suited for this application?Anyone worked on the same application please let me know.

Regards,

Srujana.

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Hello Srujana,

As per our discussion, the issue got resolved by replacing apiRetStatus = CyU3PGpifSMStart (START,ALPHA_START); with this CyU3PGpifSMStart (RESET,ALPHA_RESET);

Regards,

Rashi

Regards,
Rashi

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Rashi_Vatsa
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Hello Srujana,

We have tested the firmware and FPGA bit file which is with the application note AN 65974. It works fine for spartan 6 and Cyclone 3 FPGA.

Please program the FX3 with the .img file already there in the folder.

There are some limitations as mentioned in the readme.txt file

In synchronous burst access operation, the minimum transfer size to

perform data read/write accesses from/to the FX3 device should be three words.

In 16-bit mode this is six bytes and 32-bit mode this is twelve bytes.

To transfer data less than this, single cycle access operation needs to

be used.

Also check the functionality by following the steps mentioned in section 11.5.1 and let me know whether it works or not.

Regards,

Rashi

Regards,
Rashi
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Hello,

I am not using AN65974 firmware, I am using modified GpifToUsb firmware(PIB to SIB) in that I am replacing AN65974 state machine.I am getting data as either all bytes are 0x00 or 0xFF and not the data which is coming from FPGA.What is the problem?

Regards,

Srujana.

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Hello srujana,

Please probe the lines at GPIF interface and share the traces

Regards,

Rashi

Regards,
Rashi
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Hello,

Please find the traces attached below:

Traces.PNG

Traces_2.PNG

Regards,

Srujana.

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Hello Srujana,

Please let me know how do you check that you are getting 0x00 and 0xFF

Also share your whole firmware with the GPIF state machine

Regards,

Rashi

Regards,
Rashi
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Hello,

I am checking the data through firmware (PIB to SIB and SIB to UIB) so I am monitoring the data through In endpoint 0x82 in Control Center by passing vendor request.

Regards,

Srujana.

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Hello Srujana,

Please check that you are getting CY_U3P_SIB_EVENT_XFER_CPLT event. This event is generated when the write or read is finished.

You can track this event using a variables and print the variables value in the for{} loop.

Also confirm that writing and reading are done to/from same address.

Regards,

Rashi

Regards,
Rashi
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Hello,

I want to know whether the GPIF interface settings are correct inorder to receive data from FPGA.

Regards,

Srujana.

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Hello Srujana,

Please confirm that the GPIF bus width is 16 bits.

Can you send a full buffer (as per firmware) and check whether you get the producer event? You can put CyU3PDeviceReset(CyFalse) to check the producer event.

if (type == CY_U3P_DMA_CB_PROD_EVENT)

    {

        CyU3PDeviceReset(CyFalse);

        /* Change the first and last data bytes for tracking on a USB trace. */

        input->buffer_p.buffer[0x0000] = DataSignature++;

        input->buffer_p.buffer[input->buffer_p.count - 1] = DataSignature++;

        CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0);

    }

Producer event is generated when the buffer is full so you need to send data equal or more than than the buffer size.

The .cyfx file in the project is not the one as in An 65974 but the gpif2config.h file is updated one. From the traces, the write sequence seems fine. But we need to check that is the data being written to DMa buffer so we need to check the producer event.

Regards,

Rashi

Regards,
Rashi
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Hello,

I have one question here.

Before programming FX3,the traces are coming fine i.e...,signals and data but after programming FX3 in traces i am getting only 2 bytes of data which is in address 0x02000000.

After programming,

2.PNG

3.PNG

Before Programming FX3:

4.PNG

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Hello Srujana,

Please explain me this statement

>>Before programming FX3,the traces are coming fine i.e...,signals and data but after programming FX3 in traces i am getting only 2 bytes of data which is in address 0x02000000.

How are you able to transfer data before programming the FX3?

Also i am not able to interpret the first snapshot that you shared in your response (0x02000000). what does it mean? How do you check it? Please mention the steps you are doing while testing the data transfer .

To check whether the data is written properly to SIB block you need to check the PROD event and CONS event. Please check and let me know whether you get PROD event or not (as asked in my in previous response).

What is the data size you are transferring from PIB to SIB?

Regards,

Rashi

Regards,
Rashi
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Hello,

How are you able to transfer data before programming the FX3?

     I am not transferring data before programming the FX3,I am just checking the flags by probing them before and after programming.

Also i am not able to interpret the first snapshot that you shared in your response (0x02000000). what does it mean?

     It is the data which I am sending from FPGA side and the snapshot i attached is the memory.

Please mention the steps you are doing while testing the data transfer .

          1.Programming FX3 with .img file

          2.Programming FPGA with .bin file

          3.Checking the data in Control Center as my firmware is such that it transfers data from PIB to SIB and SIB to UIB i.e I am checking                     data which is in S0 port.

Please check and let me know whether you get PROD event or not (as asked in my in previous response).

I checked for producer events and device is resetting after programming.

What is the data size you are transferring from PIB to SIB?

4096 bytes.

My only question here is whether my GPIF interface settings are ready to read data from FPGA or not.

Regards,

Srujana.

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Hello Srujana,

Can you compare the trace after programming FX3 with the figure 4 Synchronous Slave FIFO Write Sequence (page 😎 of the application note  AN65974 and let me know the observation

As the trace you shared is not complete i can't compare at my end.If both are same then we can say the GPIF settings are fine.

Regards,

Rashi

Regards,
Rashi
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Hello,

I compared both the traces.The result is as follows:

Write Sequence.PNGILA_PROBES.PNGflagb.PNG

Regards,

Srujana.

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Hello Srujana,

1) From the traces, i found that SLWR is not going low while your are writing the data.

The write sequence mentions that SLWR should be high at first and then should be asserted low to start writing the data. Please confirm this happens correctly.

2) The full flag A (it seems flag 0 in your case) should be high at first (not full) and will be asserted low when the DMA buffer is full . The trace that you shared shows it is already low (which means DMA buffer is full).

If the DMA buffer is full, it should be committed to the consumer socket ans the data should be consumed (written to Storage port)

If both points above (1 and 2) are proper the GPIF interface would be correct.

Please check that the consumer events are generated

1) dmaCfg.notification = CY_U3P_DMA_CB_CONS_SUSP | CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;

In GpifToUsbDmaCallback function

2)   if (type == CY_U3P_DMA_CB_CONS_EVENT)

    {

        CyU3PDeviceReset(CyFalse);

        /* Data transfer has been started. Enable the LPM disable loop. */

    }

Please try this and let me know the results

Regards,

Rashi

Regards,
Rashi
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Hello,

1) From the traces, i found that SLWR is not going low while your are writing the data.

The write sequence mentions that SLWR should be high at first and then should be asserted low to start writing the data.

          Yes,but in my case it is not happening.The flags are high and SLWR is low throughout the transaction the signals are not triggering.

Please check that the consumer events are generated

          Yes,the consumer events are generating.

Regards,

Srujana.

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Hello Srujana,

Yes,but in my case it is not happening.The flags are high and SLWR is low throughout the transaction the signals are not triggering.

>> From this it seems that the FPGA is not programmed properly. The state machine of the master (FPGA ) should be as mentioned in section 11.4 of the application note AN65974

The FPGA should assert the SLWR signal low to write data to FX3. When the SLWR line is asserted the FX3 state machine would sample the data lines.

If the SLWR is not asserted through out (there should not be PROD and CONS event (as no data will be sampled).  Please check the connections again and confirm that you rae checking the PROD and CONS event correctly. ( check that there is only one CyU3PDeviceReset(CyFalse) call in the firmware either in CONS or PROD event)

Also, in your previous traces, SLWR was asserting low. To check whether the FPGA is working fine, program the FX3 with the default .img (SF_loopback.img) file in the folder with AN65974 and follow the steps mentioned in section 11.5.1 Steps to Test Loopback Transfer

Regards,

Rashi

Regards,
Rashi
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Hello,

Check that there is only one CyU3PDeviceReset(CyFalse) call in the firmware either in CONS or PROD event.

     Yes, i am checking either  PROD or CONS event only one at a time.

To check whether the FPGA is working fine, program the FX3 with the default .img (SF_loopback.img) file in the folder with AN65974

     When I program FX3 with default firmware,the device is not detecting.

Regards,

Srujana.

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Hello Srujana,

Please check the PMODE lines. Please try booting form USB

Please try programming the FX3 with the attached .img file and let me know the results

Regards,

Rashi

Regards,
Rashi
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Hello,

Please check the PMODE lines.

     Yes, I checked those lines and they are connected for Loopback transfer only.

The device is not enumerating even with above img file also.But it is enumerating for my application firmware.

Is there any default  state machine for FPGA to FX3(PIB to SIB)?

Regards,

Srujana.

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Hello Srujana,

The default firmware should work properly.

Is there any default  state machine for FPGA to FX3(PIB to SIB)

>>The .img file that i was referring to includes the default slavefifo state machine .

As we discussed that we need to check the FPGA working too, as SLWR pin is not being pull down for writing the data.

Did you check the device manager? Is the device showing up in other devices in the device manager when you program it with default .img file? Please let me know how does the device boot? Is it from USB, SPI  Flash or I2C EEPROM?

Regards,

Rashi

Regards,
Rashi
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Hello,

Please let me know how does the device boot? Is it from USB, SPI  Flash or I2C EEPROM?

     I am booting the device through USB.

The default firmware should work properly.

     Yes,but in my case it is not enumerating.Why?

Regards,

Srujana.

    

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Hello Srujana,

Please check the FPGA functionality by programming the FX3 with the firmware attached.

I checked the working with SPARTAN 6 board with USB 2.0. The firmware is configured for #define LOOPBACK_SHRT_ZLP enabled.

The clock frequency (PCLK) is 99 MHz (time period 0.010 us). The time for which SLWR gets asserted is checked form the trace. For each clock edge 2 bytes (16 bits) of data is transferred from GPIF > USB.

The mode that i have checked is full packet and then short packet. Please check the results attached

One trace shows SLWR asserting for 2.56 us. Hence 256 clock edges = 512 bytes (Bulk packet size for USB 2.0). If you are checking it on USB 3.0 it should be 1024 bytes

The other trace shows short packet. SLWR asserted for 0.16 us. 16 clock cycles = 32 bytes of data transferred.

Please check the FPGA accordingly and let me know the results.

Regards,

Rashi

Regards,
Rashi
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Hello,

I tested with the above attached firmware on my side and the traces are as below.

Since the above attached firmware is working for FPGA to FX3 at your end.Is there any problem with FPGA?Because SLWR signal is always low throughout the data transfer.

Regards,

Srujana.

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Hello Sruajana,

If before transferring the data the SLWR remains low then the FPGA is not driving the pins as mentioned in the write sequence mentioned in AN65974.

Please confirm that does the SLWR remains low before and after transferring the data. In the trace you shared the data is continuously transferred and SLWR is low (which is as expected). But what is the status of SLWR previous to data transfer. Also, flag A (flag0) is not going low (which shows DMA buffer is full), this can be because the data is not written (sampled) into the DMA buffer.

Regards,

Rashi

Regards,
Rashi
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Hello,

Please confirm that does the SLWR remains low before and after transferring the data.

    SLWR is high before transferring data and is becoming low after data transfer.

But what is the status of SLWR previous to data transfer.

     SLWR is high previous to data transfer.

Also, flag A (flag0) is not going low (which shows DMA buffer is full), this can be because the data is not written (sampled) into the DMA buffer.

     Exactly,this is what my doubt is the flags are always high after transferring data which means that DMA buffer is not full to commit the data      to S0 port.

Before Data Transfer:

FLAGA -  Low

FLAGA -  Low

SLWR  -   High

After Data Transfer:

FLAGA -  High

FLAGA -  High

SLWR  -   Low

Regards,

Srujana.

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Hello Srujana,

The project i shared doesn't have S0 port. It was just to check FPGA working.

As per the state machine in the project (shared in previous response) Please confirm you are probing FLAG A (GPIO 21).

Program the FX3 with .img file in the folder i shared and please check the by transferring data IN from Control Center and let me know the results.

slavefifo_d.PNG

Also let me know the .bit file used for FPGA programming is from the the AN 65974 or a custom one

Regards,

Rashi

Regards,
Rashi
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Hello,

The project i shared doesn't have S0 port. It was just to check FPGA working.

     Yes, I am also testing the above firmware to make sure that FPGA is working properly.Once it is done,I will run another firmware which includes S0 port from FX3  side.

Please confirm you are probing FLAG A (GPIO 21).

     Yes,I am probing FLAG A  to GPIO 21 and FLAG B  to GPIO 22.

Also let me know the .bit file used for FPGA programming is from the the AN65974 or a custom one.

     I am using Custom bit file.

Regards,

Srujana.

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Hello Srujana,

Thank you for the update

Did you check Transfer IN from the Control Center? Please let me know the results. If there is error 997 please check the PROD and CONS events are occurring or or not (by calling CyU3PDeviceReset(CyFalse);)

Regards,

Rashi

Regards,
Rashi
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Hello,

Yesterday,I checked with Slavefifo(custom) firmware with that I got data in Control center as attached in Traces_1.So,I took the same GPIF State machine and started working with firmware which includes S0 port (since my application is to store the same data in SD Card) with that I am getting only 0x00 in control centre as attached in Traces_2.

Did you check Transfer IN from the Control Center?

     Yes.

Regards,

Srujana.

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Hello Srujana,

The PIBToSIB_SibToUsb example cannot be directly used with the slave fifo state machine.

The example you are referring to uses vendor commands which sends SIBReadWrite requests to SIB Socket 0 and Socket 1 for write and read requests. Without these requests sent the data will not be written to SD card  even though the data is coming from FPGA. This is why the data is not written to SD Card.

These SIBReadWrite are called when the vendor commands are passed properly

As in the trace_2, the control out transfer failed, the vendor command is not sent properly and hence not data written to SD card. Please refer to the attachment. The control transfer should be successful.

Try sending small amount of data from FPGA and then send appropriate vendor command to write that data to SD card. After that read the data from SD card sending the vendor command for that.

Let me know the results

Regards,

Rashi

Regards,
Rashi
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Hello,

As in the trace_2, the control out transfer failed, the vendor command is not sent properly and hence not data written to SD card.

     Yes,this is the reason i am not able to write into SD Card.Thanks a lot for finding my mistake.Hope all good now!

And the last thing is.....

First I have to pass Read Request and then Write request to SD Card.And when i pass read request second time it should write sampled data into SD Card.Am I right?

When I am passing Read Request 0x98 for the first time ,I am able to get complete 4096 bytes of data and then followed by 997 error as attached.That looks fine...

When I pass Read request second time,i am not getting the sampled data  in control center.Why?

Regards,

Srujana.

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Hello Srujana,

First I have to pass Read Request and then Write request to SD Card.And when i pass read request second time it should write sampled data into SD Card.Am I right?

>> the Read request should be passed when you want the data written in SD card to be read. To write sampled data to SD card you need to send the write request.

Regards,

Rashi

Regards,
Rashi
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Hello,

With Slavefifo firmware ,I am getting exact data that is sent by FPGA.

Traces_1.PNG

With PIBToSIB_SibToUsb,I am getting some random data in Control Center

13.PNG

Regards,

Srujana.

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Srujana,

Please check the CY_U3P_SIB_EVENT_XFER_CPLT event (in CyFxMscApplnSibCB ) after you send the write request vendor command.

You can increment a variable and print the variable later in infinite for loop

if (evt == CY_U3P_SIB_EVENT_XFER_CPLT)

    {

       variable ++;

        if (status != CY_U3P_SUCCESS)

        {

            CyU3PDeviceReset(CyFalse);

            glMscCmdStatus     = 1;

            glSensePtr[portId] = CY_FX_MSC_SENSE_CRC_ERROR;

Let me know the results.

Regards,

Rashi

Regards,
Rashi
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Hello,

I tried the steps that you mentioned in the above response and the device is not resetting even by calling   CyU3PDeviceReset(CyFalse);

Slavefifo state machine will drive the data from GPIF to FX3 so I tried the same GPIF state machine with PIB_SIB firmware.The difference is only U port and S0 port (which is internal to FX3) right?Why we shouldn't use the same sate machine for PIB_SIB firmware?

Regards,

Srujana.

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Hello Srujana,

Please confirm that did this event occur (evt == CY_U3P_SIB_EVENT_XFER_CPLT). If this event occurs means that data is transferred to SIB (storage port). Did the the variable got incremented?

When the SIBReadWrite requests  is finished successfully CY_U3P_SIB_EVENT_XFER_CPLT will be generated

Regards,

Rashi

Regards,
Rashi
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Hello,

Please confirm that did this event occur (evt == CY_U3P_SIB_EVENT_XFER_CPLT).

     That event itself is not happening.

    if (evt == CY_U3P_SIB_EVENT_XFER_CPLT)

    {

    rxcount++;

        if (status != CY_U3P_SUCCESS)

        {

            CyU3PDeviceReset(CyFalse);

            glMscCmdStatus     = 1;

          

I added the above snippet in cb function and the device is not resetting,it is again enumerating as StreamerExample device only.

Did the the variable got incremented?

     No.

I got exact output from FPGA while using PIB TO UIB and with this firmware PIB TO SIB ,I am not getting where the problem is.

Regards,

Srujana.

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Hello Srujana,

Please confirm this:

Programmed FX3

Programmed FPGA

Sent 1 packet of data (512 bytes for USB 2.0 an 1024 bytes for USB 3.0)

Received the the PROD event

Sent the vendor command to write to the SD card. Send a 0x11 vendor command with wIndex (SD card Block address to write). This writes the committed buffer to SD Card

Received CY_U3P_SIB_EVENT_XFER_CPLT

Regards,

Rashi

Regards,
Rashi
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