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SuperSpeed Explorer Kit SRAM_FX3 example don't work correctly if data bus width equls 8 bit
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Hello,
Please refer to the schematic of superspeed explorer kit. This can be found in the following location:
C:\Program Files (x86)\Cypress\SuperSpeed Explorer Kit\1.0\Hardware
Please check the connection between P Port and the SRAM chip. Only 16 data pins are connected. So even if you configure the GPIF II to 32 bits, there will not be a 32 bit transmission from P Port to SRAM chip. So please dont use this example with 32 bit data bus. This example is actually designed to write and read 16 bit data from and to the SRAM chip inside the explorer kit. Please do not modify the state machine to read or write data more or less than 16 bits as you will not be getting exactly the same data that you expect.
Best Regards,
Jayakrishna
Jayakrishna
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Hello,
Please share the GPIF II designer file so that i can understand the interface between GPIF II and the memory part and the state machine that you are using. Also, please let me know which memory part you are using for this project.
Best Regards,
Jayakrishna
Jayakrishna
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Hello
I am working with the SRAM_FX3 test case that comes with
SuperSpeed Explorer Kit, which, I believe, writes to the ondoard Ram of the device from a zero address. With a data bus width of 16 and 32 bits, it works great. When I set the data bus width to 8 bits - when I read from RAM, I got the picture that I cited in a previous post
Best Regards,
Igor But
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Hello,
I believe that you are using the FX3 SRAM Master example which is provided along with FX3 SDK. This is found in the following path.
C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\gpif_examples\cyfxsrammaster
Please feel free to correct me if I'm wrong.
Note: The path depends on the installation directory of FX3 SDK.
Best Regards,
Jayakrishna
Jayakrishna
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Hello
no, I'm working with an example c:\Program Files\ Cypress\SuperSpeed Explorer Kit \1.0\ Firmware\SRAM_FX3
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although as I just saw the GPIF II state machine diagram for these examples are the same
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Hello,
Please share the GPIF II file that you used for sending 32 bit data also.
Best Regards,
Jayakrishna
Jayakrishna
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Hello,
Sorry for the confusion. Please share the GPIF II designer file when you used 32 bit data bus.
Best Regards,
Jayakrishna
Jayakrishna
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Hello,
Please refer to the schematic of superspeed explorer kit. This can be found in the following location:
C:\Program Files (x86)\Cypress\SuperSpeed Explorer Kit\1.0\Hardware
Please check the connection between P Port and the SRAM chip. Only 16 data pins are connected. So even if you configure the GPIF II to 32 bits, there will not be a 32 bit transmission from P Port to SRAM chip. So please dont use this example with 32 bit data bus. This example is actually designed to write and read 16 bit data from and to the SRAM chip inside the explorer kit. Please do not modify the state machine to read or write data more or less than 16 bits as you will not be getting exactly the same data that you expect.
Best Regards,
Jayakrishna
Jayakrishna
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Well, I understand what my mistake is. But then the following question arises for me: can I use 16 gpif pins hardware to access, with this interface, a device that has an 8-bit data bus? or is it not possible in principle?
best regards
Igor but
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Hello,
Can you please explain the application. Is it like, you need to access a device with 8 bit data bus using FX3? Or is it like, using the same code, why you cannot transfer 8 bit data even though 16 data pins are connected? Please correct me if Iam wrong.
Best Regards,
Jayakrishna
Jayakrishna
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Hello
The device, in the development of which I take part, will use FX3 to communicate with the host. The composition of this device under development will include at least two hardware units, which must be accessed via the GPIF interface. One unit - XILINX FPGA has an 8-bit data bus. The second device has a 16-bit data bus. The FX3 will use a 16-pin GPIF hardware configuration for the data bus. It’s clear to me that for these two devices you need to use different GPIF state machines, but will there be a conflict between the hardware configuration of the GPIF and the software in this case? Is it possible to implement such a solution? I hope I clearly stated my question
Best regards
Igor But
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Hello,
Please find my comment below:
As you know that when you are using 16 bit interface, the address bus will be GPIO 22-29 and when you are using 8 bit interface, the address bus will be GPIO 8-15. You can develop 2 GPIF II configurations - one for an 8 bit interface and another for a 16 bit interface. To communicate with the device having 8 bit data bus, then DQ0-DQ7 should be routed to the device's data bus and GPIO 8-15 need to be routed to the address bus. To communicate with the device having 16 bit data bus, DQ0-DQ15 should be routed to the device's data bus and GPIO 22-29 need to be routed to the device's address bus. You need to ensure both the above connections are correct so that there wont be any conflicts. Now when you want to send data to device having 8 bit data bus, load the GPIF II configurations corresponding to 8 bit interface. When you want to communicate with the device having 16 bit data bus, load the GPIF II configurations corresponding to 16 bit interface.
Best Regards,
Jayakrishna
Jayakrishna