Bugfix: synthesis error in GlitchFilter_v2_0

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StSi_284576
Level 1
Level 1
5 replies posted Welcome! First question asked

Hi Cypress Team,

there is a small syntax error in the Verilog module of GlitchFilter_v2_0. It is triggered when signal width >1 and "Bypass filter at Logic on/zero" is selected.

Attached patch will fix this.

Thank you.

1 Reply
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi Stefan,

Thanks for providing the solution to the community. We will look into this and take necessary steps.

Happy Designing !

Best Regards,
Vasanth

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