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Nov 29, 2019
02:23 AM
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Nov 29, 2019
02:23 AM
Hi Cypress Team,
there is a small syntax error in the Verilog module of GlitchFilter_v2_0. It is triggered when signal width >1 and "Bypass filter at Logic on/zero" is selected.
Attached patch will fix this.
Thank you.
- Tags:
- bug fixes
1 Reply
Dec 09, 2019
09:10 PM
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Dec 09, 2019
09:10 PM
Hi Stefan,
Thanks for providing the solution to the community. We will look into this and take necessary steps.
Happy Designing !
Best Regards,
Vasanth